Abstract: Devices and methods for reducing and/or substantially eliminating pixel charge imbalance due to variable refresh rates are provided. By way of example, a method includes providing a first frame of image data via a processor to a plurality of pixels of the display during a first frame period corresponding to a first refresh rate, and providing a second frame of image data to the plurality of pixels of the display during a second frame period corresponding to a second refresh rate. The method further includes dividing the first frame period into a first frame sub-period and a second frame sub-period, and driving the plurality of pixels of the display with the first frame of image data during the first frame sub-period and the second frame sub-period.

Abstract: The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below.

Abstract: This application relates to systems, methods, and apparatus for compensating voltage for pixels of a display panel based on the location of the pixels within the display panel. An amount of voltage compensation is assigned to each pixel or a group of pixels within the display panel in accordance with a calibration of the display panel. During operation of the display panel, pixel data is generated for a location of the display panel, and the pixel data is modified according to the amount of voltage compensation corresponding to the location. By modifying the pixel data in this way, spatial variations in voltage across the display panel can be mitigated in order to reduce the occurrence of certain display artifacts at the display panel.

Abstract: Methods and devices for reducing the power consumption of a frame buffer and timing controller of an electronic display are provided. By way of example, a method of operating an electronic display includes receiving image data from a processor of the electronic display, storing the image data to a buffer of the electronic display, reading the image data from the buffer to supply the image data to a column driver of the electronic display, determining whether an amount of image data stored in buffer is less than a threshold, and switching from reading the image data from the buffer to reading the image data directly from the processor when the amount of image data stored in buffer is less than the threshold.

Abstract: The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below.

Abstract: Systems and methods are provided to perform refresh-rate dependent dithering. One embodiment describes a computing device that includes an image source that generates spatially dithered image data and an electronic display communicatively coupled to the image source. More specifically, the electronic display receives the spatially dithered image data from the image source and determines a refresh rate with which to display an image by comparing a local histogram and an artifact histogram, in which the local histogram describes pixel grayscale distribution of a portion of the image and the artifact histogram describes a pixel grayscale distribution that when displayed will cause a perceivable artifact. Additionally, when the determined refresh rate is less than a threshold refresh rate of the electronic device, the electronic display spatially dithers the image data without temporally dithering the image data and displays the image based at least in part on the spatially dithered image data.

Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include gate driver integrated circuits. Each gate driver integrated circuit may have a shift register that supplies the gate line signals to the rows of pixels. The display driver circuitry supplies a clock signal to the gate driver integrated circuits. Each gate driver integrated circuit may have one or more clock trees that are selectively enable and disabled. Each gate driver integrated circuit may have a controller and a buffer that is controlled by a control signal from the controller. The buffer may be adjusted to supply or to not supply the clock signal to an associated clock tree in that gate driver integrated circuit.

Abstract: Methods and devices employing circuitry for dynamically adjusting bandwidth control of a display interface are provided. The display interface or image content is dynamically adjusted to support both high-speed image data (e.g., 120 Hz image data) and lower-speed content (e.g., 60 Hz content). For example, in some embodiments, additional pixel pipelines and/or processing lanes may be activated during the rendering of high-speed image data, but not during the rendering of low-speed image data. Additionally or alternatively, high-speed image data, but not low-speed data, may be compressed to render high-speed content over an interface that supports only low-speed content.

Abstract: Systems and methods for controlling operation of an electronic display are provided. One embodiment describes an electronic display, which includes a display driver that writes image frames to pixels of the electronic display with a first refresh rate or a second refresh rate; and a timing controller that receives a plurality of image frames from an image source, in which the plurality of image frames are displayed on the electronic display to play video content; detects a cadence with which the plurality of image frames are received from the image source; and, based at least in part on the cadence of the plurality of image frames, instructs the display driver to write each of the plurality of image frames either as a single image frame at the first refresh rate or an image frame at the first refresh rate followed by a repeat of the image frame at the second refresh rate.

Abstract: This application relates to performing seamless video transitions at a display panel when a video stream changes resolution and/or scale. The video stream can be provided by a host device to a timing controller (TCON). When a parameter of the video stream is going to change, the host device can cause the TCON to enter a panel self refresh (PSR) mode. During the PSR mode, the TCON can drive the display panel using an image frame stored in a memory of the TCON. Additionally, during the PSR mode, the host device can adjust a scaler and/or resolution associated with the TCON. Once the host device has finished adjusting the TCON, the TCON can exit the PSR mode and the host device can provide a new data stream to the TCON without any apparent display artifacts being output by the display panel.

Abstract: One embodiment describes an electronic display. The electronic display includes display driver circuitry that displays at least a first image frame and a second image frame on the electronic device using a first display pixel and a second display pixel. The electronic display also includes touch sensing circuitry that detects user interaction with the electronic display. A timing controller of the electronic display determines at least a first insertion time for a first intra-frame pause for the first image frame and a second insertion time for a second intra-frame pause for the second image frame. The first and second intra-frame pauses are periods where the display driver circuitry is pauses rendering of image data to allow the touch sensing circuitry to detect user interaction. The insertion times for the first and second intra-frame pauses are varied from one another.

Abstract: Devices and methods for reducing or eliminating spatiotemporal dithering image artifacts are provided. By way of example, a method includes providing positive polarity and negative polarity data signals to a plurality of pixels of a display during a first frame period, in which the first frame period corresponds a first spatiotemporal rotation phase. The method includes providing the positive polarity signals and the negative polarity signals to the plurality of pixels of the display during a second frame period, in which the second frame period corresponds a second spatiotemporal rotation phase. A spatiotemporal rotation phase sequence provided to the display comprises the first spatiotemporal rotation phase and the second spatiotemporal rotation phase. One of the first spatiotemporal rotation phase and the second spatiotemporal rotation phase of the spatiotemporal rotation phase sequence is altered during the first frame period or the second time period.

Abstract: One embodiment of the present disclosure describes an electronic display. The electronic display includes a display driver that write image frames to pixels of the electronic display with a first refresh rate or a second refresh rate, in which the second refresh rate is less than the first refresh rate. Additionally, the electronic display includes a timing controller that receives image frames from an image source, in which one or more of the image frames are configured to be displayed on the display panel to play video content; determines a capture rate of the video content based at least in part on a cadence with which the image frames are received, in which the capture rate describes a rate at which each of the one or more image frames was captured by an image sensor; and instructs the display driver to write the one or more of the image frames at the second refresh when the second refresh rate is an integer multiple of the capture rate.

Abstract: One embodiment describes an electronic display that displays image frames with a first refresh rate or a second refresh rate, in which the second refresh rate is lower than the first refresh rate; a display driver that writes the image frames by applying voltage to a display panel; and a timing controller that receives first image data from an image source, in which the first image data describes a first image frame and a first desired refresh rate equal to the second fresh rate; and that instructs the display driver to apply a first set of voltage polarities to the display panel to display first image frame at the first refresh rate and to apply a second set of voltage polarities to the display the first image frame at the second refresh rate when polarity of inversion imbalance accumulated is equal to polarity of the first set of voltage polarities.

Abstract: Systems, methods, and device are provided to perform refresh-rate dependent dithering. One embodiment of the present disclosure describes a computing device that includes an image source that generates spatially dithered image data and an electronic display communicatively coupled to the image source. More specifically, the electronic display receives the spatially dithered image data from the image source and determines a refresh rate with which to display an image by comparing a local histogram and an artifact histogram, in which the local histogram describes pixel grayscale distribution of a portion of the image and the artifact histogram describes a pixel grayscale distribution that when displayed will cause a perceivable artifact.

Abstract: System and method for improving displayed image quality of an electronic display that displays a first image frame by applying a first voltage to a display pixel and a second image frame directly before the first image frame by applying a second voltage to the display pixel. A display pipeline is communicatively coupled to the electronic display and receives first image data corresponding with the first image frame, where the image data includes a first grayscale value corresponding with the display pixel. Additionally the display pipeline determines an inversion balancing grayscale offset based at least in part on the first grayscale value when polarity of the first voltage and polarity of the second voltage are the same and determines magnitude of the first voltage by applying the inversion balancing grayscale offset to the first grayscale value to reduce likelihood of a perceivable luminance spike when displaying the first image frame.

Abstract: The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below.

Abstract: Systems, apparatuses, and methods for synchronizing backlight adjustments to frame updates in a display pipeline. A change in the ambient light is detected and as a result, backlight settings are adjusted. To offset a reduction in the backlight, the color intensity in the frames is increased. While the change in ambient light is detected asynchronously, the adjustment to the backlight settings and color intensity is synchronized to a frame update via a virtual channel for the auxiliary channel of the display interface.

Abstract: This paper describes various embodiments that relate to personal computer systems, and accurate initialization of computer hardware of personal computer systems from a low-power and/or power-off state. According to one embodiment of the invention, a computer system includes a device operative to be powered down to the power-off state dependent upon an amount of user activity on the computer system. The computer system also includes a device controller operative to initialize the device from the power-off state to a power-on state responsive to user activity on the computer system. The device controller has at least one sensor device operative to determining a physical variable related to the device, and operating characteristics of the device are related to the physical variable.

Abstract: Devices and methods for providing an indication of an active frame start, while reducing a number of line buffers utilized by conventional systems are provided herein. By way of example, an electronic display panel may include a host device (e.g., a processor) that provides an indication of a pending active frame start. The indication may be provided at a predetermined and fixed time/line interval before the active frame start. Next, a timing controller of the display circuitry may generate a vertical start pulse during vertical blanking based upon the indication and the fixed time/line interval. The vertical start pulse may be used to drive multi-clock integrated row driver circuits.