Abstract: Aspects of the disclosure relate generally to the design of the functional units of a processor core, and more specifically, to adding logical operations of a first functional unit of a processor core to a second functional unit of the processor core. In an aspect, a processor core includes a first functional unit configured to provide first functionality, wherein the first functional unit includes circuitry configured to perform a first set of logical operations, a second functional unit configured to provide second functionality different from the first functionality, wherein the second functional unit includes circuitry configured to perform a subset of logical operations of the first set of logical operations, and a data bus connecting the first functional unit and the second functional unit.

Abstract: Aspects of the disclosure relate generally to the design of the functional units of a processor core, and more specifically, to adding logical operations of a first functional unit of a processor core to a second functional unit of the processor core. In an aspect, a processor core includes a first functional unit configured to provide first functionality, wherein the first functional unit includes circuitry configured to perform a first set of logical operations, a second functional unit configured to provide second functionality different from the first functionality, wherein the second functional unit includes circuitry configured to perform a subset of logical operations of the first set of logical operations, and a data bus connecting the first functional unit and the second functional unit.

Abstract: Disclosed are techniques for processing non-vector micro-operations. In an aspect, a micro-operation processing apparatus may include a first execution unit configured to execute micro-operations and a second execution unit configured to execute micro-operations. The micro-operation processing apparatus may include a first multiplexer having an output operatively coupled to an input of the second execution unit. The micro-operation processing apparatus may include a first data input lane operatively coupled to an input of the first execution unit and a first input of the first multiplexer. The micro-operation processing apparatus may also include a second data input lane operatively coupled to a second input of the first multiplexer.