Patents by Inventor Christopher Pan

Christopher Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210323689
    Abstract: Some embodiments include a high efficiency, lightweight solar sheet. Some embodiments include a solar sheet configured for installation on a surface of a UAV or on a surface of a component of a UAV. The solar sheet includes a plurality of solar cells and a polymer layer to which the plurality of solar cells are attached. Some embodiments include a kit for supplying solar power in a battery-powered or fuel cell powered unmanned aerial vehicle (UAV) by incorporating flexible solar cells into a component of a UAV, affixing flexible solar cells to a surface of a UAV, or affixing flexible solar cells to a surface of a component of a UAV. The kit also includes a power conditioning system configured to operate the solar cells within a desired power range and configured to provide power having a voltage compatible with an electrical system of the UAV.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 21, 2021
    Inventors: Noren Pan, Raymond Chan, Haruki Miyamoto, Andree Wibowo, Mark Osowski, Christopher Youtsey, David McCallum
  • Publication number: 20210328093
    Abstract: The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film III-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film III-V compound solar cell before it is separated from the substrate. To separate the thin film III-V compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film III-V compound solar cell.
    Type: Application
    Filed: February 8, 2021
    Publication date: October 21, 2021
    Inventors: Noren Pan, Glen Hillier, Duy Phach Vu, Rao Tatavarti, Christopher Youtsey, David McCallum, Genevieve Martin
  • Patent number: 11141403
    Abstract: Novel compounds of the structural formula I, and the pharmaceutically acceptable salts thereof, are inhibitors of TarO and may be useful in the prevention, treatment and suppression of diseases mediated by TarO, such as bacterial infections, including gram negative bacterial infections and gram positive bacterial infections such as MRSA and MRSE, alone or in combination with a ?-lactam antibiotic.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: October 12, 2021
    Assignee: MERCK SHARP & DOHME CORP
    Inventors: John P. Caldwell, Ginny Dai Ho, Sookhee N. Ha, Sandra J. Koseoglu, Marc A. Labroli, Sang Ho Lee, Christina Madsen-Duggan, Mihir Mandal, Jianping Pan, Weidong Pan, Terry Roemer, Jing Su, Christopher Michael Tan, Zheng Tan, Hao Wang, Christine Yang, Shu-Wei Yang
  • Publication number: 20210227916
    Abstract: The present disclosure provides headgear protection systems for preventing or reducing work-related traumatic brain injury and/or risk. More particularly, the disclosure provides headgear systems having an air-bubble cushioning liner to improve shock absorption performance.
    Type: Application
    Filed: January 27, 2021
    Publication date: July 29, 2021
    Applicants: The United States of America, as represented by the Secretary, Department of Health and Human Servic, BOISE STATE UNIVERSITY
    Inventors: Christopher Pan, John Wu, Uwe Reischl
  • Publication number: 20210161900
    Abstract: The present disclosure comprises compositions and methods for the treatment of senescent tumor cells. In particular, compositions and methods for countering negative effects of cancer therapy-induced senescence in tumor cells are provided.
    Type: Application
    Filed: April 29, 2019
    Publication date: June 3, 2021
    Inventors: Xiao-Fan Wang, Christopher Pan, Lifeng Yuan
  • Patent number: 9634486
    Abstract: Managing power rails, including: a plurality of power rails, each power rail coupled to at least one power supply and configured to support a plurality of similarly-configured loads; and a power rail controller configured to merge and split the plurality of power rails based on total power consumption of the plurality of similarly-configured loads. The power rail management also determines the optimal power rail mode (merge/split) based on current load of each rail and adjusts the dynamic clock and voltage scaling policy, workload allocation on each core, and performance limit/throttling management according to the power rail mode.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: April 25, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Hee Jun Park, Yuancheng Christopher Pan, Christopher Kong Yee Chun
  • Patent number: 9620452
    Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: April 11, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Xiongfei Meng, Joon Hyung Chung, Yuancheng Christopher Pan
  • Patent number: 9585242
    Abstract: A package substrate is provided that includes a substrate and a capacitor. The substrate comprises a cavity penetrating a core layer and metal layers of the substrate. The capacitor comprises electrode pads and is disposed in the cavity. One of the metal layers of the substrate includes a discontinuous metal plane, and the electrode pads directly contact the discontinuous metal plane.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: February 28, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Ryan Michael Coutts, Yuancheng Christopher Pan
  • Publication number: 20170053866
    Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.
    Type: Application
    Filed: November 8, 2016
    Publication date: February 23, 2017
    Inventors: Xiongfei MENG, Joon Hyung CHUNG, Yuancheng Christopher PAN
  • Patent number: 9575095
    Abstract: Systems and methods for sensing voltage on a chip are described herein. In one embodiment, a voltage sensor comprises a voltage-controlled oscillator coupled to a voltage being sensed, and a plurality of transition detectors, wherein each of the transition detectors is coupled to a different location on the oscillator, and wherein each of the transition detectors is configured to count a number of transitions at the respective location over a time period. The voltage sensor also comprises an adder configured to add the numbers of transitions from the transition detectors to generate an output value that is approximately proportional to the voltage.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: February 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Junmou Zhang, Chuang Zhang, Yuancheng Christopher Pan, Nan Chen
  • Patent number: 9520358
    Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: December 13, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Xiongfei Meng, Joon Hyung Chung, Yuancheng Christopher Pan
  • Patent number: 9349692
    Abstract: A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: May 24, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Yuan-cheng Christopher Pan, Fifin Sweeney, Lew Go Chua-Eoan, Zhi Zhu, Junmou Zhang, Jason Gonzalez
  • Publication number: 20160133614
    Abstract: The present disclosure provides semiconductor packages and methods for fabricating semiconductor packages. The semiconductor package may comprise a semiconductor device mounted to a first substrate, a voltage regulator mounted to the first substrate and coupled to the semiconductor device, and an inductive element located on a perimeter of the semiconductor device and coupled to the voltage regulator, wherein the inductive element is formed by a plurality of interconnected conductive elements extending vertically from the first substrate.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 12, 2016
    Inventors: Shiqun GU, Ratibor RADOJCIC, Mustafa BADAROGLU, Chunlei SHI, Yuancheng Christopher PAN
  • Publication number: 20160126180
    Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.
    Type: Application
    Filed: June 19, 2015
    Publication date: May 5, 2016
    Inventors: Xiongfei MENG, Joon Hyung CHUNG, Yuancheng Christopher PAN
  • Publication number: 20160047847
    Abstract: Systems and methods for sensing voltage on a chip are described herein. In one embodiment, a voltage sensor comprises a voltage-controlled oscillator coupled to a voltage being sensed, and a plurality of transition detectors, wherein each of the transition detectors is coupled to a different location on the oscillator, and wherein each of the transition detectors is configured to count a number of transitions at the respective location over a time period. The voltage sensor also comprises an adder configured to add the numbers of transitions from the transition detectors to generate an output value that is approximately proportional to the voltage.
    Type: Application
    Filed: August 13, 2014
    Publication date: February 18, 2016
    Inventors: Junmou Zhang, Chuang Zhang, Yuancheng Christopher Pan, Nan Chen
  • Publication number: 20160013643
    Abstract: Managing power rails, including: a plurality of power rails, each power rail coupled to at least one power supply and configured to support a plurality of similarly-configured loads; and a power rail controller configured to merge and split the plurality of power rails based on total power consumption of the plurality of similarly-configured loads. The power rail management also determines the optimal power rail mode (merge/split) based on current load of each rail and adjusts the dynamic clock and voltage scaling policy, workload allocation on each core, and performance limit/throttling management according to the power rail mode.
    Type: Application
    Filed: July 9, 2014
    Publication date: January 14, 2016
    Inventors: Hee Jun Park, Yuancheng Christopher Pan, Christopher Kong Yee Chun
  • Publication number: 20150235952
    Abstract: A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.
    Type: Application
    Filed: May 4, 2015
    Publication date: August 20, 2015
    Inventors: Yuancheng Christopher Pan, Fifin Sweeney, Lew G. Chua-Eoan, Zhi Zhu, Junmou Zhang
  • Publication number: 20150237714
    Abstract: A package substrate is provided that includes a substrate and a capacitor. The substrate comprises a cavity penetrating a core layer and metal layers of the substrate. The capacitor comprises electrode pads and is disposed in the cavity. One of the metal layers of the substrate includes a discontinuous metal plane, and the electrode pads directly contact the discontinuous metal plane.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 20, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Ryan Michael Coutts, Yuancheng Christopher Pan
  • Patent number: 9048112
    Abstract: A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: June 2, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Yuancheng Christopher Pan, Fifin Sweeney, Lew G. Chua-Eoan, Zhi Zhu, Junmou Zhang
  • Patent number: 8692368
    Abstract: A stacked integrated circuit (IC) device includes a semiconductor IC having an active face, and an interconnect structure. The active face receives a regulated voltage from a voltage regulator (MEG). An active portion of the VREG, which supplies the regulated voltage to the semiconductor IC is coupled to the interconnect structure. A packaging substrate includes one or more inductors including a first set of through vias. The first set of through vias are coupled to the interconnect structure and cooperate with the active portion to provide the regulated voltage for the semiconductor IC. The IC also includes a printed circuit board (PCB) coupled to the packaging substrate. The PCB includes a second set of through vias coupled to the first set of through vias. The IC also includes one or more conducting paths on the PCB. The conducting path(s) couple together at least two through vias of the second set of through vias.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: April 8, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Yuancheng Christopher Pan, Lew G. Chua-Eoan, Zhi Zhu, Junmou Zhang