Abstract: The disclosure relates to anti-cancer compounds derived from a payload which binds to poly(ADP-ribose) polymerase (PARP) and a nuclear steroid-targeting epitope (B of Formula I), which components are covalently linked via a linker, to products containing the same, as well as to methods of their use and preparation.

Abstract: The disclosure relates to anti-cancer compounds derived from nuclear steroid receptor binders, to products containing the same, as well as to methods of their use and preparation.

Abstract: The disclosure relates to anti-cancer compounds derived from nuclear steroid receptor binders, to products containing the same, as well as to methods of their use and preparation.

Abstract: The disclosure relates to anti-cancer compounds derived from nuclear steroid receptor binders, to products containing the same, as well as to methods of their use and preparation.

Abstract: The disclosure relates to anti-cancer compounds derived from nuclear steroid receptor binders, to products containing the same, as well as to methods of their use and preparation.

Abstract: This invention comprises methods of inducing or maintaining sphincter continence, or inhibiting or alleviating incontinence, in a mammal comprising administration of a compound of the formulae I or II: wherein Z is a moiety selected from the group of: wherein: R1 is selected from H, OH or the C1-C12 esters or C1-C12 alkyl ethers thereof, benzyloxy, or halogens; or C1-C4 halogenated ethers including trifluoromethyl ether and trichloromethyl ether; R2, R3, R4, R5, and R6 are H, OH or C1-C12 esters or C1-C12 alkyl ethers thereof, halogens, or C1-C4 halogenated ethers, cyano, C1-C6 alkyl, or trifluoromethyl, with the proviso that, when R1 is H, R2 is not OH; Y is the moiety: R7 and R8 are alkyl or concatenated together to form an optionally substituted, nitrogen-containing ring; or a pharmaceutically acceptable salt thereof.

Abstract: A dual word enable method for memory data access includes the steps of: (i) providing a plurality of address data signals for addressing data stored in an array; (ii) issuing a first row access strobe (RAS) signal to decode the addressing data; and (iii) issuing a second row access strobe (RE2) signal for driving the address data into the memory array after determining that data is present in the memory array.

Abstract: This invention relates to the use of 2-substituted-1-acyl-1,2-dihydroquinoline derivatives to increase high density lipoprotein cholesterol (HDL-C) concentration and as therapeutic compositions for treating atherosclerotic conditions such as dyslipoproteinamias and coronary heart disease.

Abstract: Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring.

Abstract: A column of an integrated memory circuit includes two bit lines each with a right half and a left half and a plurality of similar memory cells connected to each half of each bit line. One of the memory cells connected to each line is used as a reference and the other cells are used for data storage. Each half of each bit line is connected to a sense node of a sense amplifier latch through an independently controlled transistor switch. To read the data from the first half of the first bit line, the transistors connecting the first half of the first bit line to the sense node is turned on and the transistor connecting the second half of the first bit line to the sense node is turned off. Both transistor switches connecting respective halves of the other bit line to the other sense node are turned on. Each half of each bit line includes approximately the same effective load. The load applied to the first sense node is thus about half of the load applied to the second sense node.

Abstract: An architecture and method of implementing an invalid data handling least recently used replacement mechanism in a cache memory system is provided that includes a first register stack, a second register stack and stack control logic. The first register stack includes registers for holding entry address information. The stack control logic includes logic for inhibiting the placement of invalidated entry addresses into a Most Recently Used register in the first register stack and directs that such invalidated entry addresses be input into the second register. The stack control logic further directs that any new entry addresses be placed in the first register stack where invalidated entry addresses has resided. A counter keeps count of the number of invalidated entry addresses input into the second register stack and toggles a multiplexer at a Least Recently Used Entry output of the first register stack to select as its output, the output of the second register stack.

Abstract: A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture includes a synchronous dynamic random access memory (SDRAM) bank including a row decoder coupled to a memory bank array for selecting a row of data in the memory bank array, sense amplifiers coupled to the memory bank array via bit lines for latching the row of data selected by the row decoder, and a synchronous column select means for selecting a desired column of the row of data. A randomly addressable row register stores a row of data latched by the sense amplifiers. A select logic gating means, disposed between the sense amplifiers and the row register, selectively gates the row of data present on the bit lines to the row register in accordance to particular synchronous memory operations of the cached SDRAM being performed. Data to be input into the cached SDRAM during a Write operation is received by the sense amplifiers and written into the memory bank array.

Abstract: Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring.