Abstract: A resource manager of a virtualized computing service indicates to a client that FPGA-enabled compute instances are supported at the service. From a set of virtualization hosts of the service, a particular host from which an FPGA is accessible is selected for the client based on an indication of computation objectives of the client. Configuration operations are performed to prepare the host for the application, and an FPGA-enabled compute instance is launched at the host for the client.

Abstract: A resource manager of a virtualized computing service indicates to a client that FPGA-enabled compute instances are supported at the service. From a set of virtualization hosts of the service, a particular host from which an FPGA is accessible is selected for the client based on an indication of computation objectives of the client. Configuration operations are performed to prepare the host for the application, and an FPGA-enabled compute instance is launched at the host for the client.

Abstract: A resource manager of a virtualized computing service indicates to a client that FPGA-enabled compute instances are supported at the service. From a set of virtualization hosts of the service, a particular host from which an FPGA is accessible is selected for the client based on an indication of computation objectives of the client. Configuration operations are performed to prepare the host for the application, and an FPGA-enabled compute instance is launched at the host for the client.

Abstract: A resource manager of a virtualized computing service indicates to a client that FPGA-enabled compute instances are supported at the service. From a set of virtualization hosts of the service, a particular host from which an FPGA is accessible is selected for the client based on an indication of computation objectives of the client. Configuration operations are performed to prepare the host for the application, and an FPGA-enabled compute instance is launched at the host for the client.

Abstract: A resource manager of a virtualized computing service indicates to a client that FPGA-enabled compute instances are supported at the service. From a set of virtualization hosts of the service, a particular host from which an FPGA is accessible is selected for the client based on an indication of computation objectives of the client. Configuration operations are performed to prepare the host for the application, and an FPGA-enabled compute instance is launched at the host for the client.

Abstract: A computer system includes compute nodes coupled through a switch to shared or non-shared I/O devices. The switch includes a pool of bridge headers and virtual bridges coupling a root port of a compute node to each of one or more shared or non-shared I/O devices. The switch is configured to associate each of the virtual bridges with a respective one of the fixed pool of bridge headers, receive a packet including data identifying the root port and a shared or non-shared I/O device, and route the packet in response to comparing data in the packet to data in the bridge headers associated with the virtual bridges. The virtual bridges comprise a hierarchy of virtual bridges in which one virtual bridge connects the root port to the remaining virtual bridges of the hierarchy. The switch may change the associations between virtual bridges and bridge headers.

Abstract: An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.

Abstract: An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.

Abstract: An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of operating system domains (OSDs) through a load-store fabric, each routing transactions between the plurality of OSDs and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint requests/completes the transactions for each of the plurality of OSDs. The core logic is coupled to the first plurality of I/O ports and the second I/O port. The core logic routes the transactions between the first plurality of I/O ports and the second I/O port. The core logic designates a corresponding one of the plurality of OSDs according to a variant of a protocol, where the protocol provides for routing of the transactions only for a single OSD.

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect (“RegPCI”) bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test (“POST”).

Abstract: An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.

Abstract: An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect (“RegPCI”) bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test (“POST”).

Abstract: A network interface controller is provided which is shareable by a plurality of operating system domains within their load-store architecture. The controller includes local resources for each of the plurality of operating system domains which allow them to communicate uniquely with the controller, and global resources which allow the controller to communicate with each of the plurality of operating systems, as well as with a network fabric. A method and apparatus is provided for distinguishing between the local and global resources, for purposes of reset and configuration. Resets received from ones of the plurality of operating system domains are treated as hot-pluggable events, and utilize a reset DLLP packet to the controller. The controller allows the reset DLLP to reset only those local resources which are associated with the operating system transmitting the reset, while preserving the other local resources.

Abstract: A Fibre Channel (FC) controller shareable by a plurality of operating system domains (OSDs) within a load-store architecture is disclosed. The controller has a FC port that obtains a plurality of FC port identifiers for association with respective ones of the OSDs. A load-store bus interface is the target of a load-store transaction on a load-store bus from each OSD. The load-store transaction includes a command to perform an I/O operation with a remote FC device. Association logic populates an S_ID field of a FC frame with the FC port identifier associated with the respective OSD that initiated the command. The FC port transmits the FC frame on the FC port to the remote FC device. In one embodiment, the controller interfaces to an Advanced Switching fabric to receive packets encapsulating load-store transactions from the OSDs. Each packet includes an identifier identifying the OSD initiating the transaction.

Abstract: A Fibre Channel controller shareable by a plurality of operating system domains (OSDs) is disclosed. The controller includes a programming interface, located within a system load-store memory map of each OSD by which the OSDs request the controller to perform I/O operations with remote FC devices. The programming interface includes a distinct control/status register (CSR) bank for each of OSD. The OSDs execute load-store instructions addressed to the programming interface to request the I/O operations. Selection logic selects as a target of each of the load-store transactions the distinct CSR bank for the OSD that executed the corresponding load-store instruction. An FC port obtains a distinct FC port identifier for each OSD and transceives FC frames with the remote FC devices using the distinct FC port identifier for each OSD in response to the I/O operation requests. In one embodiment, multiple blade servers share the controller via a shared I/O switch.

Abstract: A controller shareable by a plurality of operating system domains (OSDs) for communication on a network is disclosed. The controller includes a port for coupling to the network. The port transceives packets with the network for each of the plurality of OSDs. The controller also includes a plurality of replicated programming interfaces that each receive from a respective one of the plurality of OSDs a request to obtain a port ID for the port from the network. The controller obtains from the network a distinct port ID for each of the plurality of OSDs in response to the respective request. The request comprises one or more load-store transactions. In one embodiment, the controller is a shared Fibre Channel controller.

Abstract: A Fibre Channel (FC) controller shareable by a plurality of operating system domains (OSDs) within a load-store architecture is disclosed. The controller includes a plurality of control/status register (CSR) banks. A respective one of the CSR banks is used by each OSD to request the controller to perform I/O operations with remote FC devices. A load-store bus interface receives from a load-store bus load and store transactions from each OSD. Each transaction includes an OSD identifier identifying the OSD that initiated the transaction. The bus interface directs the transactions to the respective CSR bank based on the OSD identifier. A FC port obtains a distinct FC port identifier for each OSD and transceives FC frames with the remote FC devices using the distinct FC port identifier for each OSD in response to the I/O operation requests. In one embodiment, the controller includes a shared I/O switch coupling the OSDs thereto.

Abstract: An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus includes a first plurality of I/O ports, a second I/O port, and a plurality of port initialization logic elements. The first plurality of I/O ports is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality of I/O ports routes transactions between the plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint is configured to request/complete the transactions for each of the plurality of operating system domains. One of the plurality of port initialization logic elements is coupled to the second I/O port and remaining ones of the plurality of port initialization logic elements are each coupled to a corresponding one of the first plurality of I/O ports.

Abstract: An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and link training logic. The first plurality of I/O ports is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality of I/O ports is configured to route transactions between the plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint is configured to request/complete the transactions for each of the plurality of operating system domains. The link training logic is coupled to the second I/O port. The link training logic initializes a link between the second I/O port and the first shared input/output endpoint to support the transactions corresponding to the each of the plurality of operating system domains.