Abstract: In embodiments herein, an integrated circuit device includes a logic die with processor circuitry and a memory die coupled to the logic die. The memory die includes a first memory module comprising a first memory bank and first control circuitry, a second memory module comprising a second memory bank and second control circuitry, and a scribe line on a surface of the memory die between the first memory module and the second memory module. The first memory module is not electrically connected to the second memory module, and each memory module include through silicon vias (TSVs) to electrically connect a top side of the memory module and a bottom side of the memory module (e.g., for three-dimensional stacking in the integrated circuit device).

Abstract: An apparatus comprises a first data line coupled to a first driver; a second data line coupled to a second driver; and a crosstalk cancelation circuit comprising a third driver coupled between the first data line and the second data line, the crosstalk cancelation circuit to compensate for far end crosstalk introduced from the first data line to the second data line.