Abstract: A concurrent processing system utilizes a generalized linearly expandable data transfer bus architecture to tightly couple data processors, memory and I/O devices. The system is suitable for multiple instruction multiple data processing, and operates by transmitting and receiving complete transaction codes fully identifying the target device by specifying a process code. Data processing memories and I/O devices may be dynamically assigned to a process by specifying the process code thus providing great flexibility in utilization of system resources. Processors, memories and I/O devices are connected together by means of interfaces which are connected to a bidirectional bus. The complete data transaction preferably occurs during one clock period, although four additional clock periods are used to complete a bus transaction, namely, arbitration, match recognition, data validation and acknowledgement of receipt.