Abstract: A hybrid wideband/narrowband direct digital transceiver. In an example, the transceiver includes a first-stage downconverter configured to convert a radio frequency (RF) input analog signal to a first intermediate frequency (IF1) narrowband (NB) input analog signal; a second-stage downconverter configured to convert the IF1 NB input analog signal or a millimeter wave (mmW) input analog signal to a second intermediate frequency (IF2) NB input analog signal; one or more analog to digital converters (ADCs) configured to convert one or more of the IF1 NB input analog signal, the IF2 NB input analog signal, and the RF input analog signal to digital input signals; and a processor configured to control the first-stage downconverter to set a center frequency and bandwidth of the IF1 NB input analog signal and control the second-stage downconverter to set a center frequency and bandwidth of the IF2 NB input analog signal.

Abstract: A system includes a first enclosure, a first input transmission line within the first enclosure, a first output transmission line within the first enclosure, and first one or more die within the first enclosure and laterally between the first input and first output transmission lines. The system further includes a second enclosure including conductive material, a second input transmission line within the second enclosure, a second output transmission line within the second enclosure, and second one or more die within the second enclosure and laterally between the second input and second output transmission lines. Dimensions of the first enclosure is substantially same as (e.g., within 2%) that of the second enclosure. A length of the first input transmission line differs from a length of the second input transmission line by at least 5%, the lengths being measured in a direction parallel to the lengths of the first and second enclosures.

Abstract: A transceiver having a down-converter for converting a radio-frequency (RF) input signal to an intermediate frequency (IF) signal with an analog low latency bypass path coupled to the IF signal and configured to provide a low latency IF signal and an up-converter for converting an IF signal to an RF signal. There is a digital path coupled to the IF signal and configured to provide a digitally processed IF signal, and an up-converter for converting at least one of the low latency IF signal and the digitally processed IF signal to an RF output signal. In a further example, the down-converter and the up-converter convert to millimeter wave frequencies and filters the millimeter wave frequencies with cavity filters.

Abstract: A transceiver having a down-converter for converting a radio-frequency (RF) input signal to an intermediate frequency (IF) signal with an analog low latency bypass path coupled to the IF signal and configured to provide a low latency IF signal and an up-converter for converting an IF signal to an RF signal. There is a digital path coupled to the IF signal and configured to provide a digitally processed IF signal, and an up-converter for converting at least one of the low latency IF signal and the digitally processed IF signal to an RF output signal. In a further example, the down-converter and the up-converter convert to millimeter wave frequencies and filters the millimeter wave frequencies with cavity filters.

Abstract: A transceiver having a transceiver including a down-converter for converting a radio-frequency (RF) input signal to an intermediate frequency (IF) signal with an analog low latency bypass path coupled to the IF signal and configured to provide a low latency IF signal. There is a digital path coupled to the IF signal and configured to provide a digitally processed IF signal, and an up-converter for converting at least one of the low latency IF signal and the digitally processed IF signal to an RF output signal. In a further example, the down-converter and the up-converter convert to millimeter wave frequencies and filters the millimeter wave frequencies with cavity filters comprising quartz.

Abstract: The present disclosure provide a device, system, and method for generating, in an electrical device, a 1 bit or a 0 bit that is received in a switching circuit powered by a battery. The device, system, and method generates, in the switching circuit, a negative bias voltage and a positive bias voltage. The device, system, and method transmits the negative bias voltage and the positive bias voltage to a power amplifier. The device, system, and method turns the power amplifier from an off-state to an on-state in response to receiving the negative bias voltage. The device, system, and method amplifies, with the power amplifier, a power signal moving through power amplifier when the amplifier is in the on-state.

Abstract: The present disclosure provide a device, system, and method for generating, in an electrical device, a 1 bit or a 0 bit that is received in a switching circuit powered by a battery. The device, system, and method generates, in the switching circuit, a negative bias voltage and a positive bias voltage. The device, system, and method transmits the negative bias voltage and the positive bias voltage to a power amplifier. The device, system, and method turns the power amplifier from an off-state to an on-state in response to receiving the negative bias voltage. The device, system, and method amplifies, with the power amplifier, a power signal moving through power amplifier when the amplifier is in the on-state.