Abstract: Apparatus and methods to receive and display digital television signals are described. In one embodiment, an apparatus to receive digital television signals comprises an antenna assembly coupled to the signal processing circuitry and comprising a first antenna positioned to maximize reception in a first direction and a second antenna positioned to maximize reception in a second direction, different from the first direction, and a processor coupled to the antenna assembly and comprising a selection logic module to select an antenna to receive a digital television signal for a specific channel, and a tuning logic module to configure the antenna assembly to receive a signal via a selected antenna.

Abstract: Apparatus and methods to receive and display digital television signals are described. In one embodiment, an apparatus to receive digital television signals comprises an antenna assembly coupled to the signal processing circuitry and comprising a first antenna positioned to maximize reception in a first direction and a second antenna positioned to maximize reception in a second direction, different from the first direction, and a processor coupled to the antenna assembly and comprising a selection logic module to select an antenna to receive a digital television signal for a specific channel, and a tuning logic module to configure the antenna assembly to receive a signal via a selected antenna.

Abstract: Apparatus and methods to receive and display digital television signals are described. In one embodiment, an apparatus to receive digital television signals comprises an antenna assembly coupled to the signal processing circuitry and comprising a first antenna positioned to maximize reception in a first direction and a second antenna positioned to maximize reception in a second direction, different from the first direction, and a processor coupled to the antenna assembly and comprising a selection logic module to select an antenna to receive a digital television signal for a specific channel, and a tuning logic module to configure the antenna assembly to receive a signal via a selected antenna.

Abstract: Apparatus and methods to receive and display digital television signals are described. In one embodiment, an apparatus to receive digital television signals comprises an antenna assembly coupled to the signal processing circuitry and comprising a first antenna positioned to maximize reception in a first direction and a second antenna positioned to maximize reception in a second direction, different from the first direction, and a processor coupled to the antenna assembly and comprising a selection logic module to select an antenna to receive a digital television signal for a specific channel, and a tuning logic module to configure the antenna assembly to receive a signal via a selected antenna.

Abstract: Apparatus and methods to receive and display digital television signals are described. In one embodiment, an apparatus to receive digital television signals comprises an antenna assembly coupled to the signal processing circuitry and comprising a first antenna positioned to maximize reception in a first direction and a second antenna positioned to maximize reception in a second direction, different from the first direction, and a processor coupled to the antenna assembly and comprising a selection logic module to select an antenna to receive a digital television signal for a specific channel, and a tuning logic module to configure the antenna assembly to receive a signal via a selected antenna.

Abstract: Apparatus and methods to receive and display digital television signals are described. In one embodiment, an apparatus to receive digital television signals comprises an antenna assembly (300) coupled to the signal processing circuitry and comprising a first antenna (310A) positioned to maximize reception in a first direction and a second antenna (310B) positioned to maximize reception in a second direction, different from the first direction, and a processor (340) coupled to the antenna assembly (300) and comprising a selection logic module (132) to select an antenna to receive a digital television signal for a specific channel, and a tuning logic module (134) to configure the antenna assembly to receive a signal via a selected antenna.

Abstract: A DBS receiver front end which converts the received signal directly to the baseband representation and maintains a high performance with a new techniques for tracking and counteracting frequency drift and I/Q angular error. The DBS receiver front end comprises a tuner and a demodulator/decoder. The tuner receives a high frequency signal and converts it to a baseband signal having a frequency offset error. In one embodiment, the DBS receiver front end includes a demodulator/decoder which preserves frequency offset error tracking through a channel change. The demodulator/decoder receives the baseband signal and produces a compensation signal for canceling the frequency offset error. This is done using an element which generates a value indicative of the frequency offset error. Since the frequency offset error is independent of the selected channel, freezing the value indicative of the frequency offset error during a channel change enables a much faster acquisition of timing.

Abstract: A DBS receiver front end which converts the received signal directly to the baseband representation and maintains a high performance with a new techniques for tracking and counteracting frequency drift and I/Q angular error. The DBS receiver front end comprises a tuner and a demodulator/decoder. The tuner receives a high frequency signal and converts it to a baseband signal having a frequency offset error. In one embodiment, the DBS receiver front end includes a demodulator/decoder which receives the baseband signal and produces a compensation signal for canceling the frequency offset error. The demodulator/decoder performs the frequency-offset error compensation digitally. The demodulator/decoder includes an A/D converter which over-samples (samples at a rate of more than two samples per symbol period) the baseband signal and converts it to digital form.

Abstract: A synchronizer operates to achieve initial synchronization with a TDMA acquisition signal exhibiting a potentially large Doppler. The synchronizer collects samples of a baseband signal during a timing window. A fast Fourier transform (FFT) is performed on the samples to generate a set of spectral data. The window is moved to an identical point in a subsequent frame and the FFT repeated until a high-confidence spectral data set is obtained. If the spectral data set indicates energy concentrated around a discrete frequency, then that discrete frequency represents an estimate of the acquisition signal's frequency. The timing window's timing parameters represent a time slot estimate of the acquisition signal. If the spectral data set indicates energy spread more or less uniformly over the spectrum, then no estimates are indicated and a new window is positioned at a different point in subsequent frames.

Abstract: Distortion introduced in phase modulated RF signals by amplifiers and other signal processors is substantially reduced by modifying complex modulating signals I,Q in a way that compensates for the amplifier phase error .phi..sub.e as a function of amplifier power P. In a preferred embodiment, I, Q are combined to calculate the amplifier power level and scaled by a parameter, e.g., K1=-d.phi..sub.e /dP, to provide factor B so that compensated signals I"=AQ+BI and Q"=AI-BQ, where A is a constant, can be determined. When an RF carrier modulated by I", Q" is passed through the distorting amplifier the amplifier induced distortion is cancelled. Substantial reduction in bit error probability is obtained. The method can also be used for post-distortion correction.

Abstract: A novel high-speed bit synchronizer circuit comprises a phase detector having two phase detecting loops, each adapted to generate a partial error voltage signal which is summed together to provide a single phase voltage error signal which is employed to control a VCO in the return branch of both phase detecting loops. Each phase detecting loop comprises a comparator coupled to the input data stream and to a reference voltage to provide two outputs. An electronic switch is coupled to the output of each comparator and each switch has its partial error voltage output coupled through a summing circuit to the VCO, thus completing two phase detecting loops each adapted to generate a partial phase error signal indicative of the phase error between the input data stream and the recovered clock output of the VCO.

Abstract: Apparatus is provided for locking onto a severe doppler shifted data modulated carrier signal. A phase lock loop of the type having a data detection branch, a carrier tracking branch and a voltage controlled oscillator branch is modified to provide a summing circuit at the input of the voltage control oscillator in the voltage controlled oscillator branch. A sweep control circuit is connected to the input of the summing circuit for sweeping the voltage controlled oscillator through a range of frequencies which encompass the doppler shifted carrier frequency. An automatic frequency control circuit is connected to the input of the summing circuit for automatically disconnecting the sweep control circuit from the summing circuit when the frequency of the voltage controlled oscillator reaches a predetermined value defining a window which encompasses only the center frequency of the doppler shifted carrier frequency.

Abstract: The present invention describes a phase shift key receiver or demodulator having an A.C. couple base band automatic gain control. A pair of detectors for the automatic gain control are A.C. coupled to the output of a pair of linear analog multipliers for the purpose of eliminating DC offset signals and for minimizing thermal noise at the input of the automatic gain control circuit. The outputs of the pair of detectors connected in the data detecting branch and the carrier tracking branch of the PLL are connected to a input of the summing circuit whose output is connected to the automatic gain control loop filter. The output of the filter supplies the scaling signal employed as the scaling input to the linear analog multipliers.

Abstract: A phase detector for a multi-channel PSK receiver is provided with a plurality of phase channels. Each of the phase channels has its own comparator coupled to an electronic switch for producing signals which are the products of the analog data inputs on the phase channels. The outputs from the electronic switches are connected to positive and negative summing circuits and the output of the positive and negative summing circuits are connected to the positive and negative inputs of a differential amplifier which produce a sum of the difference of the absolute value of the analog data inputs which is employed as an error voltage signal to control the frequency of a voltage controlled oscillator in a multi-channel PSK receiver. By eliminating convention analog multipliers in the phase detector, the phase detector is capable of generating error voltage signals from analog data input signals having data rates as high as 5 gigabytes per second.

Abstract: A variable data rate receiver is provided which employs a novel phase locked loop (PLL) of the type employing a data detection loop and a tracking loop. The data detection loop is initially not coupled to the input of the voltage controlled oscillator in the tracking loop of the PLL, but is separated by an electronic switch. A phase lock detection circuit is provided which is coupled to the data detection loop and to the tracking loop for detecting the difference in the voltage error signals in the data detection loop and the tracking loop. When this error signal indicates that the tracking loop is locked on to the carrier signal the electronic switch is closed completing the phase locked loop circuit after lock on of the carrier is achieved.

Abstract: The present invention provides a high frequency lock detecting circuit for generating a signal indicative of a locked or a not locked phase tracking condition in a phase locked loop circuit. The lock detector comprises a plurality of high speed function generators two of which are coupled to the modulated data streams for indicating the phase data streams and a third high speed function generator is coupled to the voltage error signal of the phase locked loop for indicating the absence or presence of a voltage error signal. The analog outputs of the function generators are summed together in a summing circuit and applied to a differential amplifier which removes the complex modulated data products from the output of the function generators and provides a signal which is equal to the absolute value of the data signals applied to the first function generators minus the absolute value of the error signal applied by the third function generator.

Abstract: A high-speed analog multiplier circuit for multiplying two analog inputs comprises a signum generator having an X input multiplier and having an output connected to a high-speed electronic switch. A Y analog input multiplicand is also connected to the high-speed electronic switch and the output of the electronic switch is connected to a differential amplifier of the type having a positive input, a negative input and a resultant output for producing the signum function (X) times Y. The electronic switch is operated by the signum generator so that the presence of a high Q output from the signum generator is effective to connect the Y multiplicand input to the positive input of the differential amplifier and that the presence of a high Q input from the signum generator is effective to connect the Y multiplicand input to the negative input of the differential amplifier.