Abstract: Encoding and decoding of video and non-video information may include creating a second symbol from a first codeword. TERC4, TMDS and/or a guard band symbols may be generated from a portion or all of the second symbol during transmission. The TMDS symbol and/or the guard band symbol may be encoded so that they may be combined within a single symbol. At least a portion of the first codeword may be TMDS encoded to generate a TMDS symbol for transmission. TMDS encoding of at least a portion of the second symbol may also generate a TERC4 symbol and/or a guard band symbol for the transmitted signal. The second symbol and the first codeword may be generated from a portion or all of a received signal. The first codeword may be a 4-bit pre-TERC4 codeword, while the second symbol may be an 8-bit pre-TMDS symbol.

Abstract: Encoding and decoding of video and non-video information may include creating a second symbol from a first codeword. TERC4, TMDS and/or a guard band symbols may be generated from a portion or all of the second symbol during transmission. The TMDS symbol and/or the guard band symbol may be encoded so that they may be combined within a single symbol. At least a portion of the first codeword may be TMDS encoded to generate a TMDS symbol for transmission. TMDS encoding of at least a portion of the second symbol may also generate a TERC4 symbol and/or a guard band symbol for the transmitted signal. The second symbol and the first codeword may be generated from a portion or all of a received signal. The first codeword may be a 4-bit pre-TERC4 codeword, while the second symbol may be an 8-bit pre-TMDS symbol.

Abstract: Systems and methods for processing information are disclosed. The method may include creating a first symbol from a codeword. One or more of a TERC4 symbol, a TMDS symbol and/or a guard band symbol may be generated from at least a portion of the first symbol, if the one or more of the TERC4 symbol, the TMDS symbol and/or the guard band symbol is at least a portion of a signal to be transmitted. At least a portion of the codeword may be TMDS encoded to generate a TMDS symbol for the at least a portion of the signal to be transmitted. At least a portion of the first symbol may be TMDS encoded to generate a TERC4 symbol for the at least a portion of the signal to be transmitted and/or to generate a guard band symbol for the at least a portion of the signal to be transmitted.

Abstract: A dual link receiver terminates, recovers, channel aligns, and link aligns a plurality of primary link channels and a plurality of secondary link channels. The plurality of primary link channels and the plurality of secondary link channels are each received, bit recovered, synchronized, decoded, and channel aligned. Then, the plurality of primary link channels and secondary link channels are link aligned. Link alignment operations first determine a relative misalignment between the plurality of primary link channels and the plurality of secondary link channels. A primary link delay is then applied to the primary link channels and a secondary link delay is then applied to the secondary link channels. A difference between the primary link delay and the secondary link delay is based upon the misalignment between the plurality of primary link channels and the plurality of secondary link channels. An enabling circuit precludes an incorrect blanking period indication.

Abstract: Systems and methods for processing information are disclosed. The method may include creating a first symbol from a codeword. One or more of a TERC4 symbol, a TMDS symbol and/or a guard band symbol may be generated from at least a portion of the first symbol, if the one or more of the TERC4 symbol, the TMDS symbol and/or the guard band symbol is at least a portion of a signal to be transmitted. At least a portion of the codeword may be TMDS encoded to generate a TMDS symbol for the at least a portion of the signal to be transmitted. At least a portion of the first symbol may be TMDS encoded to generate a TERC4 symbol for the at least a portion of the signal to be transmitted and/or to generate a guard band symbol for the at least a portion of the signal to be transmitted.

Abstract: Encoding and decoding of video and non-video information may include creating a first symbol from a codeword. TERC4, TMDS and/or a guard band symbols may be generated from a portion or all of the first symbol during transmission. The TMDS symbol and/or the guard band symbol may be encoded so that they may be combined within a single symbol. At least a portion of the codeword may be TMDS encoded to generate a TMDS symbol for transmission. TMDS encoding of at least a portion of the first symbol may also generate a TERC4 symbol and/or a guard band symbol for the transmitted signal. The first symbol and the codeword may be generated from a portion or all of a received signal. The first codeword may be a 4-bit pre-TERC4 codeword, while the first symbol may be an 8-bit pre-TMDS symbol.

Abstract: A dual link receiver terminates, recovers, channel aligns, and link aligns a plurality of primary link channels and a plurality of secondary link channels. The plurality of primary link channels and the plurality of secondary link channels are each received, bit recovered. synchronized, decoded and channel aligned. Then, the plurality of primary link channels and secondary link channels are link aligned. Link alignment operations first determine a relative misalignment between the plurality of primary link channels and the plurality of secondary link channels. A primary link delay is then applied to the primary link channels and a secondary link delay is then applied to the secondary link channels. A difference between the primary link delay and the secondary link delay is based upon the misalignment between the plurality of primary link channels and the plurality of secondary link channels. An enabling circuit precludes an incorrect blanking period indication.

Abstract: A dual link transmitter constructed according to the present invention employs a single Phase Locked Loop (PLL) to service both a primary link and a secondary link during dual link mode operations. The structure of the dual link transmitter includes both a primary link PLL and a secondary link PLL. The primary link PLL produces a primary link clock and the secondary link PLL produces a secondary link clock. During dual single link operations, the primary link clock is used to service the primary link while the secondary link clock is used to service the secondary link. However, during dual link operations, the primary link clock is used to service both the primary link and the secondary link.

Abstract: A dual link transmitter constructed according to the present invention employs a single Phase Locked Loop (PLL) to service both a primary link and a secondary link during dual link mode operations. The structure of the dual link transmitter includes both a primary link PLL and a secondary link PLL. The primary link PLL produces a primary link clock and the secondary link PLL produces a secondary link clock. During dual single link operations, the primary link clock is used to service the primary link while the secondary link clock is used to service the secondary link. However, during dual link operations, the primary link clock is used to service both the primary link and the secondary link.

Abstract: A receiver includes clock termination circuitry that is capable of applying either a terminating impedance or a high impedance to a transmission path that carries a clock signal. When multiple of these receivers are used to service data links that share a clock signal, one of the clock termination circuits applies the terminating impedance to the transmission path that carries the clock signal while the other clock termination circuit(s) applies a high impedance to the transmission path. The receiver also includes a plurality of high rate serial bit stream buffers and a clock signal buffer along with the clock termination circuitry. In other embodiments, the receiver includes a deserializer and may include a controller. The receiver may service a dual link Digital Visual Interface.

Abstract: A deserializer that deserializes a high data rate bit stream to extract a set of bits contained therein includes a data sampler, a serial-to-parallel converter, a windowing block, and a phase error detection block. The data sampler over samples the high data rate bit stream to produce a serial group of samples corresponding to the set of bits of the high data rate bit stream. The serial-to-parallel converter couples to the data sampler and converts the serial group of samples into a parallel group of samples. The windowing block receives the parallel group of samples and produces output bits corresponding to the set of bits. The phase error detection block couples to the windowing block, detects errors in the alignment of the overlapping sampling windows of the windowing block, and directs the windowing block to adjust the operation. The phase error detection block and the windowing block compensate for bit stream jitter and intersymbol interference.

Abstract: Encoding and decoding of video and non-video information may include creating a second symbol from a first codeword. TERC4, TMDS and/or a guard band symbols may be generated from a portion or all of the second symbol during transmission. The TMDS symbol and/or the guard band symbol may be encoded so that they may be combined within a single symbol. At least a portion of the first codeword may be TMDS encoded to generate a TMDS symbol for transmission. TMDS encoding of at least a portion of the second symbol may also generate a TERC4 symbol and/or a guard band symbol for the transmitted signal. The second symbol and the first codeword may be generated from a portion or all of a received signal. The first codeword may be a 4-bit pre-TERC4 codeword, while the second symbol may be an 8-bit pre-TMDS symbol.

Abstract: A dual link transmitter constructed according to the present invention employs a single Phase Locked Loop (PLL) to service both a primary link and a secondary link during dual link mode operations. The structure of the dual link transmitter includes both a primary link PLL and a secondary link PLL. The primary link PLL produces a primary link clock and the secondary link PLL produces a secondary link clock. During dual single link operations, the primary link clock is used to service the primary link while the secondary link clock is used to service the secondary link. However, during dual link operations, the primary link clock is used to service both the primary link and the secondary link.

Abstract: A receiver includes clock termination circuitry that is capable of applying either a terminating impedance or a high impedance to a transmission path that carries a clock signal. When multiple of these receivers are used to service data links that share a clock signal, one of the clock termination circuits applies the terminating impedance to the transmission path that carries the clock signal while the other clock termination circuit(s) applies a high impedance to the transmission path. The receiver also includes a plurality of high rate serial bit stream buffers and a clock signal buffer along with the clock termination circuitry. In other embodiments, the receiver includes a deserializer and may include a controller. The receiver may service a dual link Digital Visual Interface.

Abstract: A dual link receiver terminates, recovers, channel aligns, and link aligns a plurality of primary link channels and a plurality of secondary link channels. The plurality of primary link channels and the plurality of secondary link channels are each received, bit recovered, synchronized, decoded and channel aligned. Then, the plurality of primary link channels and secondary link channels are link aligned. Link alignment operations first determine a relative misalignment between the plurality of primary link channels and the plurality of secondary link channels. A primary link delay is then applied to the primary link channels and a secondary link delay is then applied to the secondary link channels. A difference between the primary link delay and the secondary link delay is based upon the misalignment between the plurality of primary link channels and the plurality of secondary link channels. An enabling circuit precludes the beginning of a blanking period from being incorrectly indicated.

Abstract: A deserializer that deserializes a high data rate bit stream to extract a set of bits contained therein includes a data sampler, a serial-to-parallel converter, a windowing block, and a phase error detection block. The data sampler over samples the high data rate bit stream to produce a serial group of samples corresponding to the set of bits of the high data rate bit stream. The serial-to-parallel converter couples to the data sampler and converts the serial group of samples into a parallel group of samples. The windowing block receives the parallel group of samples and produces output buts corresponding to the set of bits. The phase error detection block couples to the windowing block, detects errors in the alignment of the overlapping sampling windows of the windowing block, and directs the windowing block to adjust the operation. The phase error detection block and the windowing block compensate for bits stream jitter and intersymbol interference.