Abstract: A computer system is disclosed for processing industrial Boolean satisfiability (SAT) problems. A computer implemented SAT image encoder is configured to encode a runtime industrial SAT problem into a pixelated problem image comprising a plurality of rows, wherein the runtime industrial SAT problem comprises a plurality of clauses and each row of the pixelated problem image represents a corresponding one of the clauses. A computer implemented clause embedding module is configured to encode each row of the pixelated problem image into a corresponding vector, and a computer implemented vector encoder is configured to encode the vectors into an output indicating whether the runtime industrial SAT problem is satisfiable or unsatisfiable.