Abstract: A method and apparatus for error detection are presented. The method includes looking for a data packet having a predetermined format and enabling an error-checking hardware module upon detecting an input data packet having the predetermined format. The incoming data frames are checked for errors and, if an error is found, an error flag is inserted in the data packet. The flagged data packets are stored in a memory unit with the error flag so that when the data frames are subsequently decoded, the flagged data frames are processed to fix the errors. The error detection apparatus includes a parsing module that looks for data frames having a predetermined format. When such data frames are located, an error-checking module becomes enabled and an error status flag is inserted in the data stream so that the decoder can decode the according to the error status flag.

Abstract: A cost-effective decoding apparatus that balances the flexibility of the software and performance of the hardware is presented. The decoder includes a bus, hardware modules connected to the bus and configured to execute a decoding process, and a processing unit connected to the bus, wherein the processing unit executes a decoding process by sending programmed signals to the hardware modules and responding to interrupts from the hardware components according to a set of programmed instructions. The instructions are re-programmable. As the hardware modules are configured to execute discrete tasks, the decoding process may be carried out in its entirety by sending signals to the hardware modules in the programmed order. Also presented is a method of decoding data by establishing communication with hardware modules that are each configured to execute a discrete task and activating the hardware modules in an order dictated by a computer program is also presented.