Abstract: A device comprises a first comparator to generate a first clock signal based on a reference voltage and a first voltage at an output of a switched-capacitor power converter (SCPC), and a second comparator to generate a first control signal based on the first voltage and a threshold voltage. A sensor is to generate a second control signal based on one of a level of a current of the first clock signal, or a duty cycle of the first clock signal. A frequency divider circuit is to generate a second clock signal based on the first control signal and the second control signal, and in some embodiments, further based on one of the first clock signal or a third clock signal. Controller circuitry is to operate switch circuitry of the SCPC based on the first clock signal.

Abstract: Techniques and mechanisms for facilitating a scalable delivery of current to an inductor of a voltage regulator. In an embodiment, a hardware interface of integrated circuit (IC) die accommodates coupling of the IC die to multiple inductors. The hardware interface comprises contacts which are each to couple the IC die to a respective one of the multiple inductors. A phase circuit of the IC die includes multiple cells which are each coupled to a different respective contact of a plurality of contacts of the hardware interface. A digital controller of the IC die is operable to select any of various combinations of the multiple cells each to conduct a respective current with a corresponding one of the plurality of contacts. In another embodiment, the plurality of contacts are arranged as a multi-row, multi-column array.

Abstract: A microelectronic assembly is disclosed, comprising a first integrated circuit (IC) die having electrical load circuits, first control circuits, and a second control circuit, a second IC die having powertrain (PTR) phase circuits electrically coupled to the first IC die, and inductors in a package substrate electrically coupled to the first IC die and the second IC die within a package. Individual ones of the first control circuits regulates power to a corresponding one of the electrical load circuits. The second control circuit maps the first control circuits and the PTR phase circuits. The PTR phase circuits control power to the inductors. The first control circuits, the second control circuit, the PTR phase circuits and the inductors together function as a voltage regulator configured to receive power from the package substrate at a first voltage and deliver power to the electrical load circuits at a second voltage.

Abstract: Embodiments herein relate to a current source for a waveform generator in a voltage regulator (VR). In one approach, the current source is provided as a switched-capacitor frequency-to-current converter. The current source includes a switching circuit, a continuous-time integrator, and an adaptive multi-stage filter. The switching circuit receives a clock signal which is used to control switches to provide a time-varying voltage and current. The voltage and current are low-pass filtered at the continuous-time integrator before being filtered at the adaptive multi-stage filter. An output current of the adaptive multi-stage filter is then provided as an input current to a waveform generator such as to provide a pulse-width modulation signal for driving a powertrain of the VR. In another aspect, the current source includes a switching circuit and a discrete or digital integrator.

Abstract: Embodiments herein relate to a voltage regulator (VR) circuit which includes first, second and third stages. The first stage VR can operate at a fixed voltage down-conversion ratio to provide an intermediate ground voltage for the second stage VR, which is a continuous capacitive VR (C2VR). The C2VR also receives an input voltage. The third stage VR operates at a voltage down-conversion ratio to provide an output voltage. A set of clock signals with different frequencies is made available to the first stage VR to allow the first stage VR to operate with a peak efficiency according to different stresses placed on the C2VR at different times. The down-conversion ratio of the third stage VR can also be modified during a dynamic bypass mode where the input voltage ramps down to the output voltage.

Abstract: Embodiments herein relate to a semiconductor device which includes one or more voltage regulator (VR) chiplets coupled to a package interposer, where the package interposer includes coaxial magnetic composite core inductors to provide power to one or more load die. In one possible configuration, the one or more VR chiplets are coupled to the bottom side of the package interposer, the bottom side of the package interposer is coupled to the top side of a motherboard, and the one or more load die are coupled to the top side of the package interposer. In another possible configuration, the one or more VR chiplets are coupled to the bottom side of the package interposer, the top side of the package interposer is coupled to the bottom side of a motherboard and the one or more load die are coupled to the top side of the motherboard.

Abstract: Some embodiments include an apparatus having a die including circuitry; a first conductive path located at a first side of the die; a second conductive path located at a second side of the die and coupled to the circuitry; a conductive structure extending between the first and second sides of the die, the conductive structure including a first end coupled to the first conductive path and a second end coupled to the second conductive path; and a conductive bump coupled to the conductive structure through the first conductive path.

Abstract: Embodiments herein relate to a switched capacitor power converter which reduces the leakage current through a power switch when the power switch is turned off. In one aspect, a first charge pump provides a voltage Vcc_cp which is higher than a power supply voltage Vcc, and a second charge pump provides a voltage Vss_cp which is lower than a ground voltage Vss. Transistors are used to couple the first charge pump to the control gate of a p-type power switch and to couple the second charge pump to the control gate of an n-type power switch. In another example implementation, the voltage of the power switch is pulled up or down using a bootstrap capacitor.

Abstract: Embodiments herein relate to a voltage regulator (VR) which includes a main current source (MCS), a parallel current source (PCS) which is activated when a voltage droop is detected, and a finite state machine (FSM) to manage a recovery from the voltage droop. The FSM can have a Droop state in which a droop is detected in the output voltage of the VR and the PCS provides an output current to an output node of the VR, a PCS ramp down state in which the output current of the PCS ramps down while the MCS has a boosted set point, and a voltage identifier (VID) boost ramp down state in which the set point of the MCS ramps down from the boosted set point.

Abstract: Embodiments herein relate to a switching power converter which monitors the output voltage of a power train as it varies between peaks and valleys during switching of the power train. The power train includes a high-side p-type transistor and a low-side n-type transistor. When a peak of the output voltage is positive for a number of consecutive clock cycles, a process is initiated to transition the high-side transistor from hard switching to soft switching. This involve gradually increasing a time between a turn off of the low-side transistor and a turn on of the high-side transistor. The switching power converter can include a comparator and logic circuits.

Abstract: Embodiments herein relate to a circuit which generates a sawtooth waveform based on an adaptive feedback loop that self-corrects the ramp up rate to account for variations in a device. The sawtooth waveform is obtained by repeatedly charging and discharging a capacitor according to a clock signal. The sawtooth waveform can be sampled once per clock period at a comparator which provides a corresponding binary output to a state machine. If the binary output indicates the amplitude of the sawtooth waveform is below a desired maximum voltage, the state machine outputs a code word to a digitally-controlled variable current source to increase the output current. The sawtooth waveform can be used to provide a pulse-width modulated (PWM) waveform such as for a DC-DC converter.

Abstract: Embodiments herein relate to identifying, by phase current balancing (PCB) circuitry, an indication of whether a measured current of a pulse-width modulated (PWM) signal of a plurality of PWM signals is greater than or less than an average current of the plurality of PWM signals. Embodiments further relate to adjusting, by the PCB circuitry, a bias-value of a non-modulated edge of a duty cycle of the PWM signal. Other embodiments may be described and claimed.

Abstract: An apparatus includes a power converter with an input terminal and an output terminal. The apparatus further includes a first comparator. A first input of the first comparator is coupled to the output terminal of the power converter. The apparatus further includes a reference clock generator. An output of the reference clock generator is coupled to a second input of the first comparator. An input of the reference clock generator is coupled to a frequency comparator.

Abstract: A switched capacitor voltage regulator (SCVR) design, such as a continuous capacitive voltage regulator (C2VR) design, may use capacitors and switches to provide improved cost and space efficiencies. A remote sensing circuit may be used to improve C2VR performance. By adding a remote sensing circuit to the regulation feedback loop within the C2VR circuit design, the C2VR circuit may provide improved accuracy in voltage regulation, such as by providing a correction based on the voltage error between the remote-sensed voltage and the reference target. The remote sensing circuit may also provide transient information for under-voltage detection at an output terminal. This detected transient may become an alternating current (AC) portion of the under-voltage detection threshold, which improves the ability of the C2VR circuit to provide early detection for any under-voltage fault.

Abstract: Some embodiments include a voltage regulator including a clock node to receive an input clock signal, and first and second power switching blocks coupled to the clock node. The first power switching block includes a first clock generator and first switched capacitor circuitry. The first clock generator includes clock output nodes to provide first clock signals based on the input clock signal. The first switched capacitor circuitry includes input nodes to receive first control signals generated based on the first clock signals. The second power switching block includes a second clock generator and second switched capacitor circuitry. The second clock generator includes clock output nodes to provide second clock signals based on the input clock signal. The second switched capacitor circuitry includes input nodes to receive second control signals generated based on the second clock signals.

Abstract: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to multiphase power converters and how current level outputs of each phase circuit are calibrated. The multiple phase circuits are grouped into multiple subsets, wherein one phase circuit of each subset is designated as a reference phase circuit. The reference phase circuits of each subset are calibrated together, using, for example, a closed loop daisy chain technique where each reference phase circuit calibrates their current output to the current output of the previous phase circuit, or alternatively, a current averaging technique where each reference phase circuit balances their current output to the average output of the reference phase circuits.

Abstract: Embodiments disclosed herein include inductor arrays. In an embodiment, an inductor array comprises a first inductor with a first inductance. In an embodiment, the first inductor is switched at a first frequency. In an embodiment, the inductor array further comprises a second inductor with a second inductance that is different than the first inductance. In an embodiment, the second inductor is switched at a second frequency that is different than the first frequency.

Abstract: A parallel current source may be used to improve the maximum current that can be provided by a voltage regulator. The parallel current source may be used to boost efficiency of the voltage regulator by providing additional current to the output voltage node during increased current loads. In operation, when the parallel current source detects that an output current sensed at a current sense node transgresses a current threshold level, then the parallel current source controls a variable current source to apply additional current to the output voltage node. The parallel current source enables generation of a demanded current load while reducing average current passing through individual solder bumps and other components, thereby improving component reliability. The parallel current source also the voltage regulator circuit to operate at reduced current levels that improve or maximize the power efficiency.

Abstract: A device comprises a first comparator to generate a first clock signal based on a reference voltage and a first voltage at an output of a switched-capacitor power converter (SCPC), and a second comparator to generate a first control signal based on the first voltage and a threshold voltage. A sensor is to generate a second control signal based on one of a level of a current of the first clock signal, or a duty cycle of the first clock signal. A frequency divider circuit is to generate a second clock signal based on the first control signal and the second control signal, and in some embodiments, further based on one of the first clock signal or a third clock signal. Controller circuitry is to operate switch circuitry of the SCPC based on the first clock signal.

Abstract: Techniques and mechanisms for facilitating a scalable delivery of current to an inductor of a voltage regulator. In an embodiment, a hardware interface of integrated circuit (IC) die accommodates coupling of the IC die to multiple inductors. The hardware interface comprises contacts which are each to couple the IC die to a respective one of the multiple inductors. A phase circuit of the IC die includes multiple cells which are each coupled to a different respective contact of a plurality of contacts of the hardware interface. A digital controller of the IC die is operable to select any of various combinations of the multiple cells each to conduct a respective current with a corresponding one of the plurality of contacts. In another embodiment, the plurality of contacts are arranged as a multi-row, multi-column array.