Abstract: An apparatus includes a power converter with an input terminal and an output terminal. The apparatus further includes a first comparator. A first input of the first comparator is coupled to the output terminal of the power converter. The apparatus further includes a reference clock generator. An output of the reference clock generator is coupled to a second input of the first comparator. An input of the reference clock generator is coupled to a frequency comparator.

Abstract: A switched capacitor voltage regulator (SCVR) design, such as a continuous capacitive voltage regulator (C2VR) design, may use capacitors and switches to provide improved cost and space efficiencies. A remote sensing circuit may be used to improve C2VR performance. By adding a remote sensing circuit to the regulation feedback loop within the C2VR circuit design, the C2VR circuit may provide improved accuracy in voltage regulation, such as by providing a correction based on the voltage error between the remote-sensed voltage and the reference target. The remote sensing circuit may also provide transient information for under-voltage detection at an output terminal. This detected transient may become an alternating current (AC) portion of the under-voltage detection threshold, which improves the ability of the C2VR circuit to provide early detection for any under-voltage fault.

Abstract: Some embodiments include a voltage regulator including a clock node to receive an input clock signal, and first and second power switching blocks coupled to the clock node. The first power switching block includes a first clock generator and first switched capacitor circuitry. The first clock generator includes clock output nodes to provide first clock signals based on the input clock signal. The first switched capacitor circuitry includes input nodes to receive first control signals generated based on the first clock signals. The second power switching block includes a second clock generator and second switched capacitor circuitry. The second clock generator includes clock output nodes to provide second clock signals based on the input clock signal. The second switched capacitor circuitry includes input nodes to receive second control signals generated based on the second clock signals.

Abstract: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to multiphase power converters and how current level outputs of each phase circuit are calibrated. The multiple phase circuits are grouped into multiple subsets, wherein one phase circuit of each subset is designated as a reference phase circuit. The reference phase circuits of each subset are calibrated together, using, for example, a closed loop daisy chain technique where each reference phase circuit calibrates their current output to the current output of the previous phase circuit, or alternatively, a current averaging technique where each reference phase circuit balances their current output to the average output of the reference phase circuits.

Abstract: Embodiments disclosed herein include inductor arrays. In an embodiment, an inductor array comprises a first inductor with a first inductance. In an embodiment, the first inductor is switched at a first frequency. In an embodiment, the inductor array further comprises a second inductor with a second inductance that is different than the first inductance. In an embodiment, the second inductor is switched at a second frequency that is different than the first frequency.

Abstract: A parallel current source may be used to improve the maximum current that can be provided by a voltage regulator. The parallel current source may be used to boost efficiency of the voltage regulator by providing additional current to the output voltage node during increased current loads. In operation, when the parallel current source detects that an output current sensed at a current sense node transgresses a current threshold level, then the parallel current source controls a variable current source to apply additional current to the output voltage node. The parallel current source enables generation of a demanded current load while reducing average current passing through individual solder bumps and other components, thereby improving component reliability. The parallel current source also the voltage regulator circuit to operate at reduced current levels that improve or maximize the power efficiency.

Abstract: A device comprises a first comparator to generate a first clock signal based on a reference voltage and a first voltage at an output of a switched-capacitor power converter (SCPC), and a second comparator to generate a first control signal based on the first voltage and a threshold voltage. A sensor is to generate a second control signal based on one of a level of a current of the first clock signal, or a duty cycle of the first clock signal. A frequency divider circuit is to generate a second clock signal based on the first control signal and the second control signal, and in some embodiments, further based on one of the first clock signal or a third clock signal. Controller circuitry is to operate switch circuitry of the SCPC based on the first clock signal.

Abstract: Techniques and mechanisms for facilitating a scalable delivery of current to an inductor of a voltage regulator. In an embodiment, a hardware interface of integrated circuit (IC) die accommodates coupling of the IC die to multiple inductors. The hardware interface comprises contacts which are each to couple the IC die to a respective one of the multiple inductors. A phase circuit of the IC die includes multiple cells which are each coupled to a different respective contact of a plurality of contacts of the hardware interface. A digital controller of the IC die is operable to select any of various combinations of the multiple cells each to conduct a respective current with a corresponding one of the plurality of contacts. In another embodiment, the plurality of contacts are arranged as a multi-row, multi-column array.

Abstract: Embodiments herein relate to optimizing the operation of multiple integrated circuits (ICs) operating in parallel. In one aspect, the ICs are arranged in a voltage-stacked configuration, and an operating frequency of each IC is controlled using a tunable replica circuit to stabilize its voltage drop. The tunable replica circuit mimics a critical path on the IC. In another aspect, an IC is divided into top and bottom portions which are in respective voltage domains on a substrate. The substrate include a deep n-well region for the higher voltage domain. In another aspect, a physically unclonable function (PUF) is used to generate identifiers for each IC among a multiple ICs on a board. Entropy sources of the PUF generate bits of the identifiers. Unstable entropy sources are identified and their bits are masked out.

Abstract: A microelectronic assembly is provided, comprising a first IC die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR) electrically coupled to the first IC die, a package substrate having inductors of the VR electrically coupled to the first IC die and the second IC die, and a mold compound between the first IC die and the package substrate. The VR receives power at a first voltage from the package substrate and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the second IC die is in the mold compound. In some embodiments, the mold compound and the second IC die are comprised in a discrete interposer electrically coupled to the first IC die with die-to-die interconnects and to the package substrate with die-to-package substrate interconnects.

Abstract: A microelectronic assembly is provided comprising a first integrated circuit (IC) die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR), and a third IC die comprising inductors of the VR. The third IC die is between the first IC die and the second IC die, and the VR receives power at a first voltage and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the inductors in the third IC die comprise magnetic thin films. The third IC die may be a passive die without any active elements in some embodiments. In some embodiments, the microelectronic assembly further comprises a package substrate having conductive pathways, and the second IC die is between the third IC die and the package substrate.

Abstract: A microelectronic assembly is disclosed, comprising a first integrated circuit (IC) die having electrical load circuits, first control circuits, and a second control circuit, a second IC die having powertrain (PTR) phase circuits electrically coupled to the first IC die, and inductors in a package substrate electrically coupled to the first IC die and the second IC die within a package. Individual ones of the first control circuits regulates power to a corresponding one of the electrical load circuits. The second control circuit maps the first control circuits and the PTR phase circuits. The PTR phase circuits control power to the inductors. The first control circuits, the second control circuit, the PTR phase circuits and the inductors together function as a voltage regulator configured to receive power from the package substrate at a first voltage and deliver power to the electrical load circuits at a second voltage.

Abstract: Voltage dividing circuitry is provided for use in a voltage converter for converting at least one input Direct Current, DC voltage to a plurality of output DC voltages. The voltage dividing circuitry including a voltage input port to receive an input DC voltage and an inductor having an input-side switch node and an output-side switch node. The output side switch node is connectable to one of a plurality of voltage output ports to supply a converted value of the input DC voltage as an output DC voltage. The flying capacitor interface has a plurality of switching elements and at least one flying capacitor, the flying capacitor interface to divide the input DC voltage to provide a predetermined fixed ratio of the input DC voltage at the input-side switch node of the inductor. A voltage converter and a power management integrated circuit having the voltage dividing circuitry are also provided.

Abstract: A digital self-start controller, which is functional without fuse and/or trim information. The self-start controller protects a DC-DC converter against large inrush currents and voltage overshoots, while being capable of following a variable VID (voltage identification) reference ramp imposed by the system. The self-start controller uses a relaxation oscillator to set the switching frequency of the DC-DC converter. The oscillator can be initialized using either a clock or current reference to be close to a desired operating frequency. The output of the DC-DC converter is coupled weakly to the oscillator to set the duty cycle for closed loop operation. The controller is naturally biased such that the output supply voltage is always slightly higher than a set point, eliminating the need for any process, voltage, and/or temperature (PVT) imposed trims.

Abstract: Embodiments disclosed herein include inductor arrays. In an embodiment, an inductor array comprises a first inductor with a first inductance. In an embodiment, the first inductor is switched at a first frequency. In an embodiment, the inductor array further comprises a second inductor with a second inductance that is different than the first inductance. In an embodiment, the second inductor is switched at a second frequency that is different than the first frequency.

Abstract: A digital self-start controller, which is functional without fuse and/or trim information. The self-start controller protects a DC-DC converter against large inrush currents and voltage overshoots, while being capable of following a variable VID (voltage identification) reference ramp imposed by the system. The self-start controller uses a relaxation oscillator to set the switching frequency of the DC-DC converter. The oscillator can be initialized using either a clock or current reference to be close to a desired operating frequency. The output of the DC-DC converter is coupled weakly to the oscillator to set the duty cycle for closed loop operation. The controller is naturally biased such that the output supply voltage is always slightly higher than a set point, eliminating the need for any process, voltage, and/or temperature (PVT) imposed trims.

Abstract: Embodiments herein relate to a circuit which generates a sawtooth waveform based on an adaptive feedback loop that self-corrects the ramp up rate to account for variations in a device. The sawtooth waveform is obtained by repeatedly charging and discharging a capacitor according to a clock signal. The sawtooth waveform can be sampled once per clock period at a comparator which provides a corresponding binary output to a state machine. If the binary output indicates the amplitude of the sawtooth waveform is below a desired maximum voltage, the state machine outputs a code word to a digitally-controlled variable current source to increase the output current. The sawtooth waveform can be used to provide a pulse-width modulated (PWM) waveform such as for a DC-DC converter.

Abstract: Embodiments herein relate to identifying, by phase current balancing (PCB) circuitry, an indication of whether a measured current of a pulse-width modulated (PWM) signal of a plurality of PWM signals is greater than or less than an average current of the plurality of PWM signals. Embodiments further relate to adjusting, by the PCB circuitry, a bias-value of a non-modulated edge of a duty cycle of the PWM signal. Other embodiments may be described and claimed.

Abstract: Apparatuses, methods and storage medium associated with deriving power output from an energy harvester are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a plurality of times at which an intermediate voltage of a two stage power conversion circuit corresponds to a voltage reference, and ascertain an amount of time between one of the identified times and another one of the identified times. The one or more processors, devices, and/or circuitry may derive a power or current value associated with the second power supply using the amount of time.

Abstract: In one embodiment, an energy harvesting system includes multiple-input-multiple-output switched-capacitor (MIMOSC) circuitry comprising a plurality of switched-capacitor circuit units to receive a plurality of direct current (DC) input voltages at respective input terminals of the switched-capacitor circuit unit, combine the received DC input voltages, and provide the combined DC input voltages at an output terminal of the switched-capacitor circuit unit. The energy harvesting system also includes maximum power point tracking (MPPT) circuitry coupled to switches of the switched-capacitor circuit units of the MIMOSC circuitry. The MPPT circuitry is to provide a plurality of switching signals to the switches of the switched-capacitor circuit units. The MIMOSC circuitry is to provide a plurality of DC output voltages to respective loads based on the switching signals from the MPPT circuitry.