Abstract: A position tracking system has a laser transmitter, a control tracker and a layout indicator. The laser transmitter has a laser for emitting a laser beam, a controller controlling the laser, and a motor for rotating the emitted laser beam. The control tracker has a housing, at least two photo diodes disposed on the housing, and a laser assembly for generating a beam to be projected unto a surface. The layout indicator has a housing, and at least two photo diodes disposed on the housing. A network server communicates with at least one of the laser transmitter, the control tracker and the layout indicator.

Abstract: A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value.

Abstract: A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value.