Abstract: A process for forming self-aligned cobalt silicide layers on an MOS transistor structure that reduces the risk of creating cobalt silicide bridges between source/drain regions and silicon (e.g. amorphous or polysilicon) gates. The process includes the use of an optimized argon sputter etch surface preparation step prior to cobalt layer deposition. The argon sputter etch step utilizes a DC bias of less than −278 volts in order to insure that backsputtering of silicon onto gate sidewall spacers by the argon ions is minimized. Preferred argon etch sputter steps use a DC bias of less than −80 volts, have a native silicon dioxide etch rate of no more than 5 angstroms per minute and target 20 to 60 angstroms of native silicon dioxide removal. Also provided is a process for preparing the surface of an MOS transistor or structure for subsequent cobalt layer deposition and cobalt salicide formation that includes use of an argon sputter etch process with a DC bias of less than −278 volts.