Abstract: A mold extractor is described that includes a mold support configured to contact at least a first end portion of an ice mold during use, and an extracting component configured to be manually lifted by a user to remove the ice mold from a vessel, the extracting component comprising at least one of a handle connected to the mold support with an upwardly extending gripping portion, and a flange formed at an upper end of the mold support. Corresponding systems and methods also are disclosed.

Abstract: A system and method for increasing address generation operations per cycle is described. In particular, a unified address generation scheduler queue (AGSQ) is a single queue structure which is accessed by first and second pickers in a picking cycle. Picking collisions are avoided by assigning a first set of entries to the first picker and a second set of entries to the second picker. The unified AGSQ uses a shifting, collapsing queue structure to shift other micro-operations into issued entries, which in turn collapses the queue and re-balances the unified AGSQ. A second level and delayed picker picks a third micro-operation that is ready for issue in the picking cycle. The third micro-operation is picked from the remaining entries across the first set of entries and the second set of entries. The third micro-operation issues in a next picking cycle.

Abstract: An integrated circuit device includes a first module disposed within a first power domain, a second module disposed in a second power domain that is a sub-domain of the first power domain, first power gating logic, and second power gating logic. The first power gating logic generates a first virtual power supply for the first module. The second power gating logic is powered by the first virtual power supply for generating a second virtual power supply for the second power domain.

Abstract: A method and apparatus for an efficient optical proximity correction (OPC) repair flow is disclosed. Embodiments may include receiving an input data stream of an integrated circuit (IC) design layout, performing one or more iterations of an OPC step and a layout polishing step on the input data stream, and performing a smart enhancement step if an output of a last iteration of the OPC step fails to satisfy one or more layout criteria and if a number of the one or more iterations satisfies a threshold value. Additional embodiments may include performing a pattern insertion process cross-linked with the OPC step, the pattern insertion process being a base optical rule check (ORC) process.

Abstract: A system and related method are disclosed for remotely notarizing a document and for recording digital notary logbook entries. A signatory records a video of a document signing on one device, and the video is conveyed to another device operated by the notary, with additional data for verification and to assist the notary. The notary notarizes the document physically or digitally, and enters a logbook entry together with the data from the signatory. Metadata including times and locations of data entry is added to the logbook data file.

Abstract: An integrated circuit device includes a first module disposed within a first power domain, a second module disposed in a second power domain that is a sub-domain of the first power domain, first power gating logic, and second power gating logic. The first power gating logic generates a first virtual power supply for the first module. The second power gating logic is powered by the first virtual power supply for generating a second virtual power supply for the second power domain.

Abstract: Disclosed is a method and system for an electronic notary journal, to run on a smartphone or computer or similar device. Embodiments allow for the storage in local memory or in a database of data that would go in a notary journal, plus metadata. Further embodiments record digital photographs or scans of the customer, witnesses, and documents. Video of the service itself can also be included in the data. Metadata recording the time, date, and geographical location at which the notary data was saved are incorporated with the notary data.

Abstract: A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

Abstract: A system and method for generating an illumination intensity profile of an illuminator that forms part of a projection lithography system. Radiation from the illuminator is projected towards an illumination profile mask having a plurality of apertures such that each aperture passes a distinct portion of the radiation. The intensity of each of the distinct portions of radiation is detected and assembled to form the illumination intensity profile.

Abstract: A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

Abstract: In order to determine an amount of critical dimension variation to expect across a surface of a final production wafer, a plurality of test structures are formed on a test wafer. The test structures are preferably of a type commonly found on the final production wafer and may for example, include transistors, ring oscillators, resistors and/or diodes. Electrical parameter testing of the test structures is next conducted in order to obtain one or more electrical performance values for each test structure. For example, the electrical performance values may correspond to processing speed, drive current, and/or off-state current of the test structures. A correlation between the electrical performance values and expected critical dimension variations is then performed and a report is generated providing the expected critical dimension variations across the surface of the wafer.