Patents by Inventor Christopher Talone
Christopher Talone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12009430Abstract: Residue at the base of a feature in a substrate to be etched is limited so that improved profiles may be obtained when forming vertical, narrow pitch, high aspect ratio features, for example fin field effect transistor (FinFET) gates. A thin bottom layer of the feature is formed of a different material than the main layer of the feature. The bottom material may be comprised of a material that preferentially etches and/or preferentially oxidizes as compared to the main layer. The bottom layer may comprise silicon germanium. The preferential etching characteristics may provide a process in which un-etched residuals do not remain. Even if residuals remain, after etch of the feature, an oxidation process may be performed. Enhanced oxidation rates of the bottom material allow any remaining residual to be oxidized. Plasma oxidation may be used. The oxidized material may then be removed by utilizing standard oxide removal mechanisms.Type: GrantFiled: February 5, 2020Date of Patent: June 11, 2024Assignee: Tokyo Electron LimitedInventors: Sergey Voronin, Christopher Catano, Sang Cheol Han, Shyam Sridhar, Yusuke Yoshida, Christopher Talone, Alok Ranjan
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Patent number: 11699741Abstract: In an example, a method includes depositing a first sidewall spacer layer over a substrate having a layer stack including alternating layers of a nanosheet and a sacrificial layer, and a dummy gate formed over the layer stack, the first sidewall spacer layer formed over the dummy gate. The method includes depositing a metal-containing liner over the first sidewall spacer layer; forming a first sidewall spacer along the dummy gate by anisotropically etching the metal-containing liner and the first sidewall spacer layer; performing an anisotropic etch back process to form a plurality of vertical recesses in the layer stack; laterally etching the layer stack and form a plurality of lateral recesses between adjacent nanosheets; depositing a second sidewall spacer layer to fill the plurality of lateral recesses; and etching a portion of the second sidewall spacer layer to expose tips of the nanosheet layers.Type: GrantFiled: June 1, 2021Date of Patent: July 11, 2023Assignee: Tokyo Electron LimitedInventors: Yusuke Yoshida, Sergey Voronin, Christopher Talone, Alok Ranjan
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Publication number: 20220384607Abstract: In an example, a method includes depositing a first sidewall spacer layer over a substrate having a layer stack including alternating layers of a nanosheet and a sacrificial layer, and a dummy gate formed over the layer stack, the first sidewall spacer layer formed over the dummy gate. The method includes depositing a metal-containing liner over the first sidewall spacer layer; forming a first sidewall spacer along the dummy gate by anisotropically etching the metal-containing liner and the first sidewall spacer layer; performing an anisotropic etch back process to form a plurality of vertical recesses in the layer stack; laterally etching the layer stack and form a plurality of lateral recesses between adjacent nanosheets; depositing a second sidewall spacer layer to fill the plurality of lateral recesses; and etching a portion of the second sidewall spacer layer to expose tips of the nanosheet layers.Type: ApplicationFiled: June 1, 2021Publication date: December 1, 2022Inventors: Yusuke Yoshida, Sergey Voronin, Christopher Talone, Alok Ranjan
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Patent number: 11398386Abstract: In one example, a method of processing a substrate includes receiving a substrate in a processing chamber, the substrate having an etch mask positioned over an underlying layer to be etched, where the underlying layer is a silicon-containing layer. The method includes executing a first etch process that includes forming a first plasma from a first process gas that includes hydrogen bromide or chlorine and etching the underlying layer using products of the first plasma. The method includes executing a second etch process that includes forming a second plasma from a second process gas that includes fluorine and etching the substrate using products from the second plasma. The method may include alternating between the first etch process and the second etch process.Type: GrantFiled: February 18, 2020Date of Patent: July 26, 2022Assignee: Tokyo Electron LimitedInventors: Yusuke Yoshida, Sergey Voronin, Shyam Sridhar, Caitlin Philippi, Christopher Talone, Alok Ranjan
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Patent number: 11133194Abstract: A method of etching a substrate includes generating plasma comprising a first concentration of an etchant and a second concentration of an inhibitor and etching the substrate by exposing an exposed interface between a first material and a second material to the plasma. The first material includes a lower reactivity to both the etchant and the inhibitor than the second material. The first concentration is less than the second concentration. Etching the substrate includes etching the first material and the second material at the exposed interface to form an etched indentation including an enriched region of the second material, forming a passivation layer at the enriched region using the inhibitor, and etching the first material at the etched indentation. The passivation layer reduces an etch rate of the second material to a reduced rate that is less than an etch rate of the first material.Type: GrantFiled: February 20, 2020Date of Patent: September 28, 2021Assignee: Tokyo Electron LimitedInventors: Sergey Voronin, Christopher Catano, Nicholas Joy, Alok Ranjan, Christopher Talone
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Patent number: 10903077Abstract: Embodiments are described herein that form silicon germanium nano-wires while reducing or eliminating erosion of nitride layers (e.g., masks and spacers) caused during selective etching of silicon with respect to silicon germanium during formation of silicon germanium nano-wires. oxide layers are used to protect nitride layers during formation of silicon germanium (SiGe) nano-wires. In particular, multilayer spacers including oxide/nitride/oxide layers are formed to protect the nitride layers during selective silicon etch processes that are used to form silicon germanium nano-wires, for example, for field effect transistors (FETs). The multilayer spacers allow for target levels of erosion to be achieved for the nitride layers.Type: GrantFiled: July 15, 2019Date of Patent: January 26, 2021Assignee: TOKYO ELECTRON LIMITEDInventors: Yusuke Yoshida, Christopher Catano, Christopher Talone, Nicholas Joy, Sergey Voronin
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Patent number: 10811273Abstract: Provided is a method of modifying a surface of a substrate for improved etch selectivity of nitride etching. In an embodiment, the method includes providing a substrate with a nitride-containing structure, the nitride-containing structure having an oxygen-nitrogen layer. The method may also include performing a surface modification process on the nitride-containing structure with the oxygen-nitrogen layer using one or more gases, the surface modification process generating a cleaned nitride-containing structure. Additionally, the method may include performing a nitride etch process using the cleaned nitride-containing structure, wherein the etched nitride-containing structure are included in 5 nm or lower technology nodes, and the nitride etch process meets target etch rate and target etch selectivity, and the cleaned nitride-containing structure meet target residue cleaning objectives.Type: GrantFiled: September 11, 2018Date of Patent: October 20, 2020Assignee: Tokyo Electron LimitedInventors: Christopher Talone, Erdinc Karakas, Andrew Nolan, Sergey A. Voronin, Alok Ranjan
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Publication number: 20200273711Abstract: In one example, a method of processing a substrate includes receiving a substrate in a processing chamber, the substrate having an etch mask positioned over an underlying layer to be etched, where the underlying layer is a silicon-containing layer. The method includes executing a first etch process that includes forming a first plasma from a first process gas that includes hydrogen bromide or chlorine and etching the underlying layer using products of the first plasma. The method includes executing a second etch process that includes forming a second plasma from a second process gas that includes fluorine and etching the substrate using products from the second plasma. The method may include alternating between the first etch process and the second etch process.Type: ApplicationFiled: February 18, 2020Publication date: August 27, 2020Inventors: Yusuke Yoshida, Sergey Voronin, Shyam Sridhar, Caitlin Philippi, Christopher Talone, Alok Ranjan
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Publication number: 20200273992Abstract: Residue at the base of a feature in a substrate to be etched is limited so that improved profiles may be obtained when forming vertical, narrow pitch, high aspect ratio features, for example fin field effect transistor (FinFET) gates. A thin bottom layer of the feature is formed of a different material than the main layer of the feature. The bottom material may be comprised of a material that preferentially etches and/or preferentially oxidizes as compared to the main layer. The bottom layer may comprise silicon germanium. The preferential etching characteristics may provide a process in which un-etched residuals do not remain. Even if residuals remain, after etch of the feature, an oxidation process may be performed. Enhanced oxidation rates of the bottom material allow any remaining residual to be oxidized. Plasma oxidation may be used. The oxidized material may then be removed by utilizing standard oxide removal mechanisms.Type: ApplicationFiled: February 5, 2020Publication date: August 27, 2020Inventors: Sergey Voronin, Christopher Catano, Sang Cheol Han, Shyam Sridhar, Yusuke Yoshida, Christopher Talone, Alok Ranjan
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Publication number: 20200266070Abstract: A method of etching a substrate includes generating plasma comprising a first concentration of an etchant and a second concentration of an inhibitor and etching the substrate by exposing an exposed interface between a first material and a second material to the plasma. The first material includes a lower reactivity to both the etchant and the inhibitor than the second material. The first concentration is less than the second concentration. Etching the substrate includes etching the first material and the second material at the exposed interface to form an etched indentation including an enriched region of the second material, forming a passivation layer at the enriched region using the inhibitor, and etching the first material at the etched indentation. The passivation layer reduces an etch rate of the second material to a reduced rate that is less than an etch rate of the first material.Type: ApplicationFiled: February 20, 2020Publication date: August 20, 2020Inventors: Sergey Voronin, Christopher Catano, Nicholas Joy, Alok Ranjan, Christopher Talone
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Publication number: 20200027736Abstract: Embodiments are described herein that form silicon germanium nano-wires while reducing or eliminating erosion of nitride layers (e.g., masks and spacers) caused during selective etching of silicon with respect to silicon germanium during formation of silicon germanium nano-wires. oxide layers are used to protect nitride layers during formation of silicon germanium (SiGe) nano-wires. In particular, multilayer spacers including oxide/nitride/oxide layers are formed to protect the nitride layers during selective silicon etch processes that are used to form silicon germanium nano-wires, for example, for field effect transistors (FETs). The multilayer spacers allow for target levels of erosion to be achieved for the nitride layers.Type: ApplicationFiled: July 15, 2019Publication date: January 23, 2020Inventors: Yusuke Yoshida, Christopher Catano, Christopher Talone, Nicholas Joy, Sergey Voronin
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Patent number: 10529540Abstract: Methods and systems for treating a substrate are described. In an embodiment, a method may include receiving a microelectronic substrate in a plasma processing chamber. A method may also include receiving process gas in the plasma processing chamber. Additionally, a method may include applying energy to the process gas with a first energy source and applying energy to the process gas with a second energy source. The method may further include selectively adjusting at least one of the first energy source and the second energy source between a first state and a second state.Type: GrantFiled: March 29, 2018Date of Patent: January 7, 2020Assignee: Tokyo Electron LimitedInventors: Sergey Voronin, Christopher Talone, Alok Ranjan
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Patent number: 10529589Abstract: A method of etching is described. The method providing a substrate having a first material composed of silicon-containing organic material and a second material that is different from the first material, forming a chemical mixture by plasma-excitation of a process gas containing SF6 and an optional inert gas, controlling a processing pressure at or above 100 mtorr, and exposing the first material on the substrate to the chemical mixture to selectively etch the first material relative to the second material.Type: GrantFiled: June 1, 2018Date of Patent: January 7, 2020Assignee: TOKYO ELECTRON LIMITEDInventors: Erdinc Karakas, Li Wang, Andrew Nolan, Christopher Talone, Shyam Sridhar, Alok Ranjan, Hiroto Ohtake
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Patent number: 10490404Abstract: Systems and methods for in situ hard mask removal are described. In an embodiment, a method includes receiving a semiconductor workpiece comprising a substrate, an intermediary layer, a hard mask layer, and a photoresist layer in an etch chamber. The method may also include etching the hard mask layer to open a region left exposed by the photoresist layer. Additionally, such an embodiment may include etching the intermediary layer in a region left exposed by the hard mask layer. The method may also include removing the hard mask layer. In such embodiments, etching the hard mask layer, etching the intermediary layer, and removing the hard mask layer are performed in the etch chamber, and without the wafer being removed from the etch chamber.Type: GrantFiled: September 19, 2017Date of Patent: November 26, 2019Assignee: Tokyo Electron LimitedInventors: Christopher Talone, Andrew Nolan, Mingmei Wang, Alok Ranjan
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Publication number: 20190304750Abstract: Methods and systems for treating a substrate are described. In an embodiment, a method may include receiving a microelectronic substrate in a plasma processing chamber. A method may also include receiving process gas in the plasma processing chamber. Additionally, a method may include applying energy to the process gas with a first energy source and applying energy to the process gas with a second energy source. The method may further include selectively adjusting at least one of the first energy source and the second energy source between a first state and a second state.Type: ApplicationFiled: March 29, 2018Publication date: October 3, 2019Inventors: Sergey Voronin, Christopher Talone, Alok Ranjan
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Publication number: 20190080926Abstract: Provided is a method of modifying a surface of a substrate for improved etch selectivity of nitride etching. In an embodiment, the method includes providing a substrate with a nitride-containing structure, the nitride-containing structure having an oxygen-nitrogen layer. The method may also include performing a surface modification process on the nitride-containing structure with the oxygen-nitrogen layer using one or more gases, the surface modification process generating a cleaned nitride-containing structure. Additionally, the method may include performing a nitride etch process using the cleaned nitride-containing structure, wherein the etched nitride-containing structure are included in 5 nm or lower technology nodes, and the nitride etch process meets target etch rate and target etch selectivity, and the cleaned nitride-containing structure meet target residue cleaning objectives.Type: ApplicationFiled: September 11, 2018Publication date: March 14, 2019Inventors: Christopher Talone, Erdinc Karakas, Andrew Nolan, Sergey A. Voronin, Alok Ranjan
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Patent number: 10204832Abstract: Provided is a method of patterning structures on a substrate using an integration scheme in a patterning system, the method comprising: disposing a substrate in a processing chamber, the substrate having a plurality of structures and a pattern, the substrate including an underlying layer and a target layer, at least one structure intersecting with another structure, each intersection having an intersection angle and a corner, the integration scheme requiring a vertical corner profile at each intersection; alternatingly and sequentially etching and cleaning the substrate to transfer the pattern onto the target layer and to achieve a target vertical corner profile at each intersection; controlling selected two or more operating variables of the integration scheme in the alternating and sequential etching and cleaning operations in order to achieve target integration objectives.Type: GrantFiled: September 19, 2017Date of Patent: February 12, 2019Assignee: Tokyo Electron LimitedInventors: Sergey A. Voronin, Christopher Talone, Alok Ranjan
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Publication number: 20180358233Abstract: A method of etching is described. The method providing a substrate having a first material composed of silicon-containing organic material and a second material that is different from the first material, forming a chemical mixture by plasma-excitation of a process gas containing SF6 and an optional inert gas, controlling a processing pressure at or above 100 mtorr, and exposing the first material on the substrate to the chemical mixture to selectively etch the first material relative to the second material.Type: ApplicationFiled: June 1, 2018Publication date: December 13, 2018Inventors: Erdinc Karakas, Li Wang, Andrew Nolan, Christopher Talone, Shyam Sridhar, Alok Ranjan, Hiroto Ohtake
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Publication number: 20180082903Abstract: Provided is a method of patterning structures on a substrate using an integration scheme in a patterning system, the method comprising: disposing a substrate in a processing chamber, the substrate having a plurality of structures and a pattern, the substrate including an underlying layer and a target layer, at least one structure intersecting with another structure, each intersection having an intersection angle and a corner, the integration scheme requiring a vertical corner profile at each intersection; alternatingly and sequentially etching and cleaning the substrate to transfer the pattern onto the target layer and to achieve a target vertical corner profile at each intersection; controlling selected two or more operating variables of the integration scheme in the alternating and sequential etching and cleaning operations in order to achieve target integration objectives.Type: ApplicationFiled: September 19, 2017Publication date: March 22, 2018Inventors: Sergey A. Voronin, Christopher Talone, Alok Ranjan
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Publication number: 20180082842Abstract: Systems and methods for in situ hard mask removal are described. In an embodiment, a method includes receiving a semiconductor workpiece comprising a substrate, an intermediary layer, a hard mask layer, and a photoresist layer in an etch chamber. The method may also include etching the hard mask layer to open a region left exposed by the photoresist layer. Additionally, such an embodiment may include etching the intermediary layer in a region left exposed by the hard mask layer. The method may also include removing the hard mask layer. In such embodiments, etching the hard mask layer, etching the intermediary layer, and removing the hard mask layer are performed in the etch chamber, and without the wafer being removed from the etch chamber.Type: ApplicationFiled: September 19, 2017Publication date: March 22, 2018Inventors: Christopher Talone, Andrew Nolan, Mingmei Wang, Alok Ranjan