Patents by Inventor Christopher Tan
Christopher Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240178145Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.Type: ApplicationFiled: February 6, 2024Publication date: May 30, 2024Inventors: Kristof DARMAWIKARTA, Hiroki TANAKA, Robert MAY, Sameer PAITAL, Bai NIE, Jesse JONES, Chung Kwang Christopher TAN
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Patent number: 11995486Abstract: Computer-implemented methods and systems for integrating computer applications are disclosed. One method includes querying a primary computer application for current state of a newly created object; receiving the current state of the object, and generating object data for a secondary computer application based on the current state of the object. The method further includes communicating an object creation request to a secondary computer application, the object creation request including the generated object data, receiving a secondary computer application object identifier from the secondary computer application upon creation of the object at the secondary computer application, and communicating the secondary computer application object identifier to the primary computer application for storing in a record of the object created at the primary computer application.Type: GrantFiled: March 6, 2023Date of Patent: May 28, 2024Assignees: ATLASSIAN PTY LTD., ATLASSIAN US, INC.Inventors: Michael Cooper, Emma Young, Liron Deutsch, Rohan Fleming, Iris Zhang, Daniel Brockwell, Jacob Bass, Duy Nguyen, Gerry Tan, Daniel Kostrzynski, Dmitry Gonchar, Jason Thai, Banu Prakash Jaya Rama Reddy, Shiveen Pandita, Julian Green, Kimmi Rawsthorne, Christopher Mann, Akhil Ojha
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Patent number: 11932746Abstract: The present invention relates to stabilising compositions, particularly stabilising compositions which can be used to stabilise insulation or semi-conductive compositions, such as are used for electrically insulating wires and cables. The stabilising composition comprises: a first stabilising component comprising at least one fully hindered phenolic antioxidant; a second stabilising component comprising at least one partially hindered phenolic antioxidant; and a third stabilising component comprising at least one sulphur-containing antioxidant.Type: GrantFiled: November 25, 2014Date of Patent: March 19, 2024Assignee: SI Group, Inc.Inventors: Jonathan Hill, Siren Tan, Christopher Rider
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Patent number: 11929330Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.Type: GrantFiled: April 4, 2022Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Kristof Darmawikarta, Hiroki Tanaka, Robert May, Sameer Paital, Bai Nie, Jesse Jones, Chung Kwang Christopher Tan
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Publication number: 20240071777Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, a method for forming an IC package support may include forming a first dielectric material having a surface; forming a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees relative to the surface of the first dielectric material; forming a second dielectric material, having a surface, on the first dielectric material; and forming a second conductive via in the second dielectric material, wherein the second conductive via is electrically coupled to the first conductive via, has tapered sidewalls with an angle that is greater than 80 degrees relative to the surface of the second dielectric material, and a maximum diameter between 2 microns and 20 microns.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: Intel CorporationInventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
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Publication number: 20240052300Abstract: The present disclosure provides materials and methods identifying, selecting, and characterizing cells that express and secrete non-Fc containing biomolecules.Type: ApplicationFiled: December 21, 2021Publication date: February 15, 2024Inventors: Glenn Christopher Tan, Ewelina Zasadzinska, Patrick Hoffmann, Bin Wu
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Patent number: 11854834Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.Type: GrantFiled: February 22, 2022Date of Patent: December 26, 2023Assignee: Intel CorporationInventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
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Patent number: 11676891Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: GrantFiled: June 30, 2021Date of Patent: June 13, 2023Assignee: Intel CorporationInventors: Hongxia Feng, Dingying David Xu, Sheng C. Li, Matthew L. Tingey, Meizi Jiao, Chung Kwang Christopher Tan
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Publication number: 20230086042Abstract: A method of facilitating a growth assessment for a cell line includes generating an image of a well that contains a medium that was inoculated with at least one cell of the cell line. The method also includes generating a down-sampled segmentation map comprising pixels that indicate an inferred presence or absence of a cell colony in corresponding portions of the well image. Generating the down-sampled segmentation map includes inputting the well image to a fully convolutional neural network having a plurality of convolutional layers. The method also includes (i) determining, by inputting colony size information (including the down-sampled segmentation map and/or a pixel count derived therefrom) to a cell growth assessment algorithm, a growth classification or score for the cell line, and causing a display of the growth classification or score, and/or (II) causing a display of the colony size information to facilitate a manual cell growth assessment.Type: ApplicationFiled: March 4, 2021Publication date: March 23, 2023Inventors: Yu Yuan, Tony Y. Wang, Kim H. Le, Christopher Tan, Jasmine Tat, Thorsten Dzidowski
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Publication number: 20230022714Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: ApplicationFiled: September 29, 2022Publication date: January 26, 2023Inventors: Hongxia Feng, Dungying David Xu, Sheng C. Li, Matthew L. Tingey, Meizi Jiao, Chung Kwang Christopher Tan
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Publication number: 20220223527Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.Type: ApplicationFiled: April 4, 2022Publication date: July 14, 2022Inventors: Kristof DARMAWIKARTA, Hiroki TANAKA, Robert MAY, Sameer PAITAL, Bai NIE, Jesse JONES, Chung Kwang Christopher TAN
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Publication number: 20220181166Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.Type: ApplicationFiled: February 22, 2022Publication date: June 9, 2022Applicant: Intel CorporationInventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
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Patent number: 11322444Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.Type: GrantFiled: March 23, 2018Date of Patent: May 3, 2022Assignee: Intel CorporationInventors: Kristof Darmawikarta, Hiroki Tanaka, Robert May, Sameer Paital, Bai Nie, Jesse Jones, Chung Kwang Christopher Tan
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Patent number: 11309192Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.Type: GrantFiled: June 5, 2018Date of Patent: April 19, 2022Assignee: Intel CorporationInventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
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Publication number: 20210327800Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: ApplicationFiled: June 30, 2021Publication date: October 21, 2021Inventors: Hongxia FENG, Dingying David XU, Sheng C. LI, Matthew L. TINGEY, Meizi JIAO, Chung Kwang Christopher TAN
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Patent number: 11088062Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: GrantFiled: July 19, 2017Date of Patent: August 10, 2021Assignee: Intel CorporationInventors: Hongxia Feng, Dingying David Xu, Sheng C. Li, Matthew L. Tingey, Meizi Jiao, Chung Kwang Christopher Tan
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Publication number: 20190371621Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.Type: ApplicationFiled: June 5, 2018Publication date: December 5, 2019Applicant: Intel CorporationInventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
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Publication number: 20190295951Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.Type: ApplicationFiled: March 23, 2018Publication date: September 26, 2019Inventors: Kristof DARMAWIKARTA, Hiroki TANAKA, Robert MAY, Sameer PAITAL, Bai NIE, Jesse JONES, Chung Kwang Christopher TAN
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Publication number: 20190027431Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: ApplicationFiled: July 19, 2017Publication date: January 24, 2019Inventors: Hongxia FENG, Dingying David XU, Sheng C. LI, Matthew L. TINGEY, Meizi JIAO, Chung Kwang Christopher TAN
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Patent number: D1026941Type: GrantFiled: March 6, 2018Date of Patent: May 14, 2024Assignee: Apple Inc.Inventors: Jody Akana, Molly Anderson, Bartley K. Andre, Shota Aoyagi, Anthony Michael Ashcroft, Marine C. Bataille, Jeremy Bataillou, Daniele De Iuliis, Markus Diebel, M. Evans Hankey, Julian Hoenig, Richard P. Howarth, Jonathan P. Ive, Julian Jaede, Duncan Robert Kerr, Peter Russell-Clarke, Benjamin Andrew Shaffer, Mikael Silvanto, Christopher J. Stringer, Joe Tan, Clement Tissandier, Eugene Antony Whang, Rico Zörkendörfer