Abstract: Apparatuses, systems, and techniques to optimize kernel selection for performing a computation. In at least one embodiment, a neural network is trained and utilized to generate a list of kernels so that an (e.g., optimal) kernel may be identified. The neural network receives characteristics of the input matrices and determines relevancy scores for a list of possible kernels. Based on an ordered listing of kernels by relevant score, a kernel is selected from the list and utilized to perform the computation and provide the result.

Abstract: Apparatuses, systems, and techniques to optimize kernel selection for performing a computation. In at least one embodiment, a neural network is trained and utilized to generate a list of kernels so that an (e.g., optimal) kernel may be identified. The neural network receives characteristics of the input matrices and determines relevancy scores for a list of possible kernels. Based on an ordered listing of kernels by relevant score, a kernel is selected from the list and utilized to perform the computation and provide the result.

Abstract: Embodiments of the present invention may be directed to a graphics system of a computer system. The system may include a frame buffer having a number of partitions respectively mapped to a number of discrete memory devices and a dedicated copy buffer operable to store new image frames, mapped to a first memory device. The first memory device corresponds to a first partition of the number of partitions. The system may also include a loader circuit coupled between the frame buffer and the dedicated copy buffer, operable to copy new image frames from the frame buffer to the dedicated copy buffer. The system may also include a clocked output coupled to receive an image frame from the dedicated copy buffer and operable to drive a display device therewith. The system may enter a low power state wherein a number of the discrete memory devices are powered off.

Abstract: A method and apparatus for performing display image refresh in bursts to a display device. A buffered refresh controller includes capabilities to drive the display based on video signals generated from a local frame buffer at a first rate. The graphics controller may optimally be configured to burst a new frame of pixel data to the buffered refresh controller at a second rate to replace the previous frame of pixel data in the local frame buffer. The second rate is different than the first rate. Additionally, the graphics controller may send frames only when they contain new pixel data. By enabling the graphics controller to selectively transmit the new frame of pixel data at the second rate, higher than the first rate, the graphics controller may be placed in a power-saving state during at least a portion of each frame update.

Abstract: Embodiments of the present invention may be directed to a graphics system of a computer system. The system may include a frame buffer having a number of partitions respectively mapped to a number of discrete memory devices and a dedicated copy buffer operable to store new image frames, mapped to a first memory device. The first memory device corresponds to a first partition of the number of partitions. The system may also include a loader circuit coupled between the frame buffer and the dedicated copy buffer, operable to copy new image frames from the frame buffer to the dedicated copy buffer. The system may also include a clocked output coupled to receive an image frame from the dedicated copy buffer and operable to drive a display device therewith. The system may enter a low power state wherein a number of the discrete memory devices are powered off.

Abstract: A method and apparatus for performing display image refresh in bursts to a display device. A buffered refresh controller includes capabilities to drive the display based on video signals generated from a local frame buffer at a first rate. The graphics controller may optimally be configured to burst a new frame of pixel data to the buffered refresh controller at a second rate to replace the previous frame of pixel data in the local frame buffer. The second rate is different than the first rate. Additionally, the graphics controller may send frames only when they contain new pixel data. By enabling the graphics controller to selectively transmit the new frame of pixel data at the second rate, higher than the first rate, the graphics controller may be placed in a power-saving state during at least a portion of each frame update.

Abstract: Apparatus and methods are disclosed for processing memory transaction requests and memory transaction results between multiple processors and multiple shared memories, where the communications path between the multiple processors and shared memories is provided by a multi-stage crossbar network comprising a plurality of serially interconnected crossbar switches, wherein each of the crossbar switches independently assigns local memory transaction identifiers to each memory transaction request that it processes and uses the local memory transaction identifiers to match each received memory transaction result with its corresponding previously processed memory transaction request.

Abstract: A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar; a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch crossbars each connected to a processor crossbar in each processor group, wherein no two switch crossbars in a switch group are connected to the same processor crossbar; a plurality of memory groups having a plurality of memory switch chips each having a plurality of memory controllers and a memory crossbar, each memory controller connected to the memory crossbar, each memory crossbar in each memory group connected to all of the switch crossbar in a corresponding one of the switch groups, wherein no two memory groups are connected to the same switch group.

Abstract: A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar; a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch crossbars each connected to a processor crossbar in each processor group, wherein no two switch crossbars in a switch group are connected to the same processor crossbar; a plurality of memory groups having a plurality of memory switch chips each having a plurality of memory controllers and a memory crossbar, each memory controller connected to the memory crossbar, each memory crossbar in each memory group connected to all of the switch crossbar in a corresponding one of the switch groups, wherein no two memory groups are connected to the same switch group.