Abstract: Systems and methods for implementing test case generation with feedback are disclosed. An exemplary system for test case generation with feedback comprises a plurality of knobs identifying test values for a device under test. A plurality of buckets is each associated with at least one of the test values, each bucket having a weight value for the associated test value. A failure analysis module is operatively associated with the device under test, the failure analysis module changing at least some weight values based on feedback from test operations for the device under test. A test case generator selects test values for test operations based on the weight value for the associated test value.

Abstract: A system and method for evaluating a multiprocessor system having multiple processors coupled via a system bus is disclosed. A test vector is executed on a processor under test. While the test vector is being executed, an instruction that causes a transaction to be issued on the system bus is executed on another processor, thereby stressing the first processor.

Abstract: A scheme for testing an electrical device to determine a range of combinations of values of N parametric variables, i.e., a SHMOO plot, for which the device functions properly. In one embodiment, the method comprises defining an N-dimensional plot region comprising a plurality of operating points each corresponding to a particular combination of values of the N parametric variables. The plot region is successively subdivided into smaller sub-regions, based on determining whether the electrical device passes or fails upon testing at each operating point of a predetermined subset of operating points of the plot region or one of the smaller sub-regions, until a minimum resolution is achieved.

Abstract: One embodiment comprises testing an electrical device using a combination of values of first and second parameters corresponding to a selected operating point comprising an origin of an R, ? polar coordinate plane; if the electrical device is determined to function in a passing manner at the selected operating point, updating the value of the polar coordinate R by incrementing the value thereof by a predetermined amount ?R; otherwise, updating the value of the polar coordinate R by decrementing the value thereof by ?R; if the updated value of the polar coordinate R is determined to be beyond an edge of a defined plot region, updating the value of the polar coordinate ? by a predetermined amount ??; and identifying an operating point corresponding to at least one of the updated values of the polar coordinates R and ?.

Abstract: A scheme for testing an electrical device to determine a range of combinations of values of N parametric variables, i.e., a SHMOO plot, for which the device functions properly. In one embodiment, the method comprises defining an N-dimensional plot region comprising a plurality of operating points each corresponding to a particular combination of values of the N parametric variables. The plot region is successively subdivided into smaller sub-regions, based on determining whether the electrical device passes or fails upon testing at each operating point of a predetermined subset of operating points of the plot region or one of the smaller sub-regions, until a minimum resolution is achieved.

Abstract: A method of testing an electrical device to determine a range of combinations of values of N variable operating parameters for which the device functions properly is described. In one embodiment, The method comprises defining a plot region comprising a plurality of operating points each corresponding to a particular combination of values of the N variable operating parameters, selecting an operating point within the plot region, testing the device using the combination of values of the N variable operating parameters corresponding to the selected operating point, and if the device functions in a first manner at the selected operating point, adding all operating points of the plot region having a first relationship with respect to the selected operating point to a list of operating points to be tested.

Abstract: A system and a method of testing an electrical device to determine a range of combinations of values of N parameters for which the device functions properly are described. In one embodiment, the method comprises subdividing a plot region comprising a plurality of operating points each corresponding to a particular combination of values of the N parameters into at least two partially overlapping sub-regions; testing the electrical device using the combination of values of the N variable parameters corresponding to the operating points located in each corner of each sub-region; and for each sub-region with respect to which the device does not function in the same manner at each corner operating point thereof, repeating the incrementing, subdividing and testing.

Abstract: A system and method for providing data coherency during the evaluation of a multiprocessor system is disclosed. A test vector generator is operable to cause a series of instructions marked with program flow indicators that affect a value stored in a virtual register space to be executed on the multiprocessor system. A progress register is associated with the virtual register space for storing a flag indicative of which instruction is to be executed with respect to the virtual register space.

Abstract: A method of testing an electrical device to determine a range of combinations of values of N variable operating parameters for which the device functions properly is described. In one embodiment, The method comprises defining a plot region comprising a plurality of operating points each corresponding to a particular combination of values of the N variable operating parameters, selecting an operating point within the plot region, testing the device using the combination of values of the N variable operating parameters corresponding to the selected operating point, and if the device functions in a first manner at the selected operating point, adding all operating points of the plot region having a first relationship with respect to the selected operating point to a list of operating points to be tested.

Abstract: A system and a method of testing an electrical device to determine a range of combinations of values of N parameters for which the device functions properly are described. In one embodiment, the method comprises subdividing a plot region comprising a plurality of operating points each corresponding to a particular combination of values of the N parameters into at least two partially overlapping sub-regions; testing the electrical device using the combination of values of the N variable parameters corresponding to the operating points located in each corner of each sub-region; and for each sub-region with respect to which the device does not function in the same manner at each corner operating point thereof, repeating the incrementing, subdividing and testing.

Abstract: A method of testing an electrical device to determine a range of combinations of values of first and second parameters to determine an operating range thereof is described. In one embodiment, the method comprises testing the device using a combination of values of the first and second parameters corresponding to a selected operating point comprising an origin of an R, &thgr; polar coordinate plane; if the device functions in a first manner at the selected operating point, updating the value of the polar coordinate R by incrementing the value thereof by a predetermined amount &Dgr;R; otherwise, updating the value of the polar coordinate R by decrementing the value thereof by &Dgr;R; and identifying an operating point corresponding to the updated values of the polar coordinates R and &thgr;.

Abstract: A system and method for evaluating a multiprocessor system having multiple processors coupled via a system bus is disclosed. A test vector is executed on a processor under test. While the test vector is being executed, an instruction that causes a transaction to be issued on the system bus is executed on another processor, thereby stressing the first processor.