Abstract: Disclosed is a digital communication control system having a serial bus buffer that includes a primary interface adapted to support serial communication over a primary bus, a buffered interface adapted to support serial communication over a buffered bus, and a controller coupled between the primary bus and the buffered bus. The primary bus is coupled to a first device and at least one second device and the buffered bus is coupled to at least one third device. The controller is adapted to receive a first data signal and a clock signal at the primary interface and replicate the first data signal and the clock signal at the buffered interface.

Abstract: The present disclosure relates to RF front-end (RFFE) circuitry that includes multiple RFFE circuits, each of which may be provided by a separate integrated circuit (IC), front-end module, or both. As such, the RFFE circuits may be connected to one another using an RFFE serial communications bus. Further, one or more of the RFFE circuits may need an accurate clock source for analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), calibration, sensor measurements, or the like. Instead of including an integral clock source circuit or receiving a separate external clock signal, an RFFE circuit may extract clock information from the RFFE serial communications bus to provide one or more clock signals. The clock information may be associated with one or more serial communications commands via the RFFE serial communications bus, may be associated with alternate functionality of the RFFE serial communications bus, or both.

Abstract: A direct current (DC)-DC converter, which includes an open loop ripple cancellation circuit, a switching supply, and a parallel amplifier, is disclosed. During a calibration mode, the parallel amplifier provides a parallel amplifier output current to regulate a power supply output voltage based on a calibration setpoint. The switching supply drives the parallel amplifier output current toward zero using a switching control signal, such that during the calibration mode, an estimate of a current gain is based on the switching control signal. Further, during the calibration mode, the open loop ripple cancellation circuit is disabled. During a normal operation mode, the open loop ripple cancellation circuit provides a ripple cancellation current, which is based on the estimate of the current gain.

Abstract: The present disclosure relates to RF front-end (RFFE) circuitry that includes multiple RFFE circuits, each of which may be provided by a separate integrated circuit (IC), front-end module, or both. As such, the RFFE circuits may be connected to one another using an RFFE serial communications bus. Further, one or more of the RFFE circuits may need an accurate clock source for analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), calibration, sensor measurements, or the like. Instead of including an integral clock source circuit or receiving a separate external clock signal, an RFFE circuit may extract clock information from the RFFE serial communications bus to provide one or more clock signal. The clock information may be associated with one or more serial communications command via the RFFE serial communications bus.

Abstract: A power management system, which includes a parallel amplifier circuit and a switch mode power supply converter, is disclosed. The switch mode power supply converter cooperatively operates with the parallel amplifier circuit to form the power management system. The power management system operates in one of a high power modulation mode, a medium power modulation mode, and a low power average power tracking mode. Further, during the high power modulation mode and the medium power modulation mode, the power management system controls a power amplifier supply voltage to a radio frequency power amplifier to provide envelope tracking. During the low power average power tracking mode, the power management system controls the power amplifier supply voltage to the radio frequency power amplifier to provide average power tracking.

Abstract: A system and method for performing sample rate conversion and creating fractional delays to a signal is disclosed. The system comprises a filter, a look up table for storing coefficients for sample rate conversion and fractional delays, and control circuitry configured to use an indexing scheme to select one or more coefficients from the look up table for rate conversion and fractional delays. The coefficients stored in the look up table comprise the coefficients required to generate delays in desired increments of a sample rate. In the disclosed method, the one or more coefficients necessary for a desired sample rate and fractional delay are selected from a single look up table and provided to a filter to delay the signal based upon the input sample rate.

Abstract: The present disclosure relates to RF front-end (RFFE) circuitry that includes multiple RFFE circuits, each of which may be provided by a separate integrated circuit (IC), front-end module, or both. As such, the RFFE circuits may be connected to one another using an RFFE serial communications bus. Further, one or more of the RFFE circuits may need an accurate clock source for analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), calibration, sensor measurements, or the like. Instead of including an integral clock source circuit or receiving a separate external clock signal, an RFFE circuit may extract clock information from the RFFE serial communications bus to provide one or more clock signals. The clock information may be associated with one or more serial communications commands via the RFFE serial communications bus, may be associated with alternate functionality of the RFFE serial communications bus, or both.

Abstract: The present disclosure relates to RF front-end (RFFE) circuitry that includes multiple RFFE circuits, each of which may be provided by a separate integrated circuit (IC), front-end module, or both. As such, the RFFE circuits may be connected to one another using an RFFE serial communications bus. Further, one or more of the RFFE circuits may need an accurate clock source for analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), calibration, sensor measurements, or the like. Instead of including an integral clock source circuit or receiving a separate external clock signal, an RFFE circuit may extract clock information from the RFFE serial communications bus to provide one or more clock signal. The clock information may be associated with one or more serial communications command via the RFFE serial communications bus, may be associated with alternate functionality of the RFFE serial communications bus, or both.

Abstract: An architecture for a radio frequency (RF) front-end is disclosed. The architecture for the RF front-end includes a circuit module that includes a plurality of dies partitioned on the circuit module. A plurality of filter banks with individual ones of the plurality of filter banks disposed on each of the plurality of circuit dies is also included. Further included is a plurality of switches having individual ones of the plurality of switches coupled to corresponding ones of the plurality of filter banks and in at least one embodiment a control system is configured to open and close selected ones of the plurality of switches.

Abstract: A protection system and method for protecting a direct current to direct current voltage converter (DC-DC converter) from a potentially damaging excessive output current due to exposure to a relatively strong magnetic field is disclosed. The system includes a detector circuit configured to monitor a signal characteristic of the DC-DC converter, and a linear regulator having an output coupled to the load output of the DC-DC converter. The system further includes a control system configured to disable a load output of the DC-DC converter and enable the output of the linear regulator when the detector detects that the signal characteristic has moved outside a predetermined threshold range. Moreover, the control system is further configured to disable the output of the linear regulator after a predetermined time period, and enable the load output of the DC-DC converter after the predetermined time period.

Abstract: A system and method for performing sample rate conversion and creating fractional delays to a signal is disclosed. The system comprises a filter, a look up table for storing coefficients for sample rate conversion and fractional delays, and control circuitry configured to use an indexing scheme to select one or more coefficients from the look up table for rate conversion and fractional delays. The coefficients stored in the look up table comprise the coefficients required to generate delays in desired increments of a sample rate. In the disclosed method, the one or more coefficients necessary for a desired sample rate and fractional delay are selected from a single look up table and provided to a filter to delay the signal based upon the input sample rate.

Abstract: An automatically configurable 2-wire/3-wire serial communications interface (AC23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. The SOS detection circuitry provides an indication of detection of the SOS to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal upon the detection of the SOS. As such, the AC23SCI automatically configures itself for operation with some 2-wire and some 3-wire serial communications buses without external intervention.

Abstract: A configurable 2-wire/3-wire serial communications interface (C23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. In response to detecting the SOS, the SOS detection circuitry provides an SOS detection signal to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal. The received sequence is associated with one of multiple serial communications protocols.

Abstract: A modulation system and method are provided for transitioning between modulation formats in adjacent transmit bursts. The modulation system includes a data interface, first modulation circuitry operating according to a first modulation format, and second modulation circuitry operating according to a second modulation format. During a transition, a timing signal triggers ramp-down of an output power of a power amplifier amplifying modulated data for the first transmit burst. Upon receiving the timing signal, the data interface proceeds to provide a current symbol of data for the first transmit burst. Upon completion of the current symbol, the data interface delays data for a second transmit burst by a variable delay time prior to providing the data for the second transmit burst to the second modulation circuitry, and the second modulation circuitry is reset. Accordingly, a glitch caused by resetting the second modulation circuitry occurs before ramp-up for the second transmit burst.

Abstract: A system and method are provided for transitioning between modulation formats in adjacent transmit bursts. The system includes a modulation system having a data interface, first modulation circuitry operating according to a first modulation format, and second modulation circuitry operating according to a second modulation format. During a transition between a first transmit burst in the first modulation format and a second transmit burst in the second modulation format, the data interface receives a timing signal signifying a start of data for the second transmit burst. In response to the timing signal, the second modulation circuitry resets, and the data interface delays the data for the second transmit burst by a modulator delay time. By delaying the data for the second transmit burst, a glitch caused by resetting the second modulation circuitry arrives at the output of the second modulation circuitry prior to the data for the second transmit burst.

Abstract: The present invention provides a system for adjusting a selectable capacitance of a variable capacitance array to compensate for voltage non-linearity of the variable capacitance array. In general, the system includes the variable capacitance array and a calibration circuit. The calibration circuit operates to determine a voltage across the variable capacitance array and to generate a capacitance selection signal based on the voltage across the variable capacitance array and a known capacitance versus voltage characteristic of the variable capacitance array.