Abstract: An apparatus includes a single sense pin connected to a line of a device connected to the apparatus, a gate pin configured to produce a gate signal to enable or disable a switch connected between the line of the device connected to the apparatus and a system ground, and control logic. The control logic is configured to at the single sense pin, determine a short between the device and the system ground, and, based upon the determination of the short, disable the switch.

Abstract: A system-level design generator tool enables users to configure system-level designs made up of electrical components that satisfy design parameters and have corresponding dependencies, e.g., power, communication, control, security, clock and memory. A block diagram representing each of the functions within the system may utilize a guided parametric search or a design tool to create the solution for each individual block. The inputs into that search and/or design tool may come from the system-level choices, constraints, and cross dependencies tracked by the system generator tool.

Abstract: An apparatus includes a single sense pin connected to a line of a device connected to the apparatus, a gate pin configured to produce a gate signal to enable or disable a switch connected between the line of the device connected to the apparatus and a system ground, and control logic. The control logic is configured to at the single sense pin, determine a short between the device and the system ground, and, based upon the determination of the short, disable the switch.

Abstract: A floating-gate transistor array and method for programming the same. The floating-gate transistor array includes a plurality of transistors having a source, drain, and floating-gate, whereby the plurality of transistors is arranged into multiple rows and columns. Each row of transistors includes a row programming switch having an output connected to each floating-gate within the row, while each column of transistors includes a column programming switch having an output connected to each drain within the column. The source of each transistor is coupled with a source line corresponding to the specific row of the transistor. The row and column programming switches are utilized to select and program a desired floating-gate transistor. In an indirect programming method, two transistors share a floating gate, such that programming a programmer transistor modifies the current of an agent transistor, which is attached to the circuit, thereby permitting run-time programming.

Abstract: A large-scale field-programmable analog array (FPAA) for rapidly prototyping analog systems and an arbitrary analog waveform generator. The large-scale FPAA includes a floating-gate transistor array and a plurality of computational analog blocks (CABs), which may be adapted to set bias voltages for operational transconductance amplifiers (OTAs), adjust corner frequencies on the capacitively coupled current conveyors, set multiplier coefficients in vector-matrix multipliers, and a variety of other operations. The floating-gate transistors may be used as switch elements, programmable resistor elements, precision current sources, and programmable transistors. Accordingly, the floating-gate transistors within the array allow on-chip programming of the characteristics of the computational elements, while still maintaining compact CABs. The arbitrary analog waveform generator may include programmable floating-gate MOS transistors for use as analog memory cells to store samples of the waveforms.