Patents by Inventor Christopher Van Beek

Christopher Van Beek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130016720
    Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 17, 2013
    Inventors: Chih-Cheh Chen, Michael T. Klinglesmith, David M. Lee, John Zulauf, Itay Franko, Peter J. Elardo, Mohan K. Nair, Christopher Van Beek
  • Patent number: 8270405
    Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: September 18, 2012
    Assignee: Intel Corporation
    Inventors: Chih-Cheh Chen, Michael T. Klinglesmith, David M. Lee, John Zulauf, Itay Franko, Peter J. Elardo, Mohan K. Nair, Christopher Van Beek
  • Publication number: 20100329254
    Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 30, 2010
    Applicant: INTEL CORPORATION
    Inventors: Chih-Cheh Chen, Michael T. Klinglesmith, David M. Lee, John Zulauf, Itay Franko, Peter J. Elardo, Mohan K. Nair, Christopher Van Beek
  • Patent number: 6134632
    Abstract: A computer system including a slice-addressable multi-port memory array is disclosed. The slice-addressable multi-port memory array provides a mechanism for efficient data merging in a memory controller in accordance with an associated array of slice-enable bits. Each slice of the memory array is individually designated by a slice-enable bit, and only those slices of a word line enabled for writing that are designated by a slice-enable bit are modified during a write operation. In a subsequent write-merge operation, the slices of the word line enabled for writing that were not designated by slice-enable bits during the write operation are modified, and the slices that were modified during the preceding write operation are unaffected, thereby providing for efficient merger of data from the write operation and data from the write-merge operation in a single word line.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: October 17, 2000
    Assignee: Intel Corporation
    Inventors: Lily Pao Looi, Sin Tan, John Urbanski, Christopher Van Beek