Abstract: Apparatuses, methods, and systems for performing sense operations in memory are disclosed. The memory can have a group of memory cells, and circuitry can be configured to perform a sense operation on the group, wherein performing the sense operation includes performing a first sense operation in a first polarity on the group of memory cells to determine a quantity of the memory cells of the group that are in a particular data state, and performing a second sense operation in a second polarity on the group of memory cells to determine a data state of the memory cells of the group. The second polarity is opposite the first polarity, and the second sense operation is a count-based sense operation that uses the determined quantity of memory cells in the particular data state as a counting threshold to determine the data state of the memory cells of the group.

Abstract: The present disclosure relates generally to a column cover comprising a first portion comprising a first side panel having a first edge and a second edge, a second side panel having a first edge and a second edge, a front panel extending between the second edge of the first side panel and the second edge of the second side panel, and an outer surface having at least one textured contour that replicates a natural building material. The cover further comprises a second portion comprising a first side panel having a first edge and a second edge, wherein the first side panel of the second portion is substantially coplanar with the first side panel of the first portion, wherein the first edge of the first side panel of the first portion is spaced apart from the first edge of the first side panel of the second portion.

Abstract: Methods, systems, and devices for shared decoder architecture for three-dimensional memory arrays are described. A memory device may include pillars coupled to an access line using two transistors positioned between the pillar and the access line. The gates of the two transistors may be coupled with respective gate lines coupled with circuitry configured to bias the gate line as part of an access operation for a memory cell coupled with the pillar. In some cases, the circuitry may be positioned between tiles of the memory device, at an end of one or more tiles of the memory device, between word line combs of a tile of the memory device, or a combination thereof.

Abstract: Methods, systems, and devices for architecture-based power management for a memory device are described. Aspects include operating a first memory bank within a memory device in a first mode and a second memory bank within the memory device in a second mode. The memory device may receive a power down command for the first memory bank while operating the first memory bank in the first mode and the second memory bank in the second mode and switch the first memory bank from the first mode to a first low power mode while maintaining the second memory bank in the second mode. The first low power mode corresponds to less power consumption by the first memory bank than the first mode. In some cases, switching the first memory bank from the first mode to the first low power mode includes deactivating circuitry dedicated to the first memory bank.

Abstract: An electronic wind instrument includes capacitance touch switch key touches, a breath pressure sensor, and pinky key touches configured specifically for the purpose of transposing musical phrases into any of the 12 musical keys.

Abstract: Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.

Abstract: The present disclosure relates to a memory device comprising an array including a plurality of memory cells and an operating unit, the operating unit comprising an encoding unit configured to store user data in a plurality of memory cells of the memory array and to store parity data associated with the user data in a number of parity cells of the memory array, the operating unit further comprising a decoding unit in turn comprising a syndrome generating unit configured to calculate an ECC syndrome from the stored user data and parity data, wherein the syndrome generating unit comprises a plurality of circuit portions, each circuit portion being configured to calculate a respective syndrome portion of the ECC syndrome.

Abstract: A method to perform data scrub operations by operating a memory device, the memory device comprising a main memory, an internal Error Correction Code (ECC) engine and a scrub memory. The method comprising: receiving a read command; accessing, based on the receiving the read command, a location in the main memory to read data at the location; error correcting data read during the accessing; and storing at the scrub memory information of the location based at least in part on the correcting the data meeting or exceeding an ECC threshold.

Abstract: The present disclosure relates to providing multiple error correction code protection levels in memory. One device includes an array of memory cells and an operating circuit for managing operation of the array. The operating circuit comprises an encoding unit configured to generate a codeword for a first error correction code (ECC) protection level and a second ECC protection level, and decoding unit configured to perform an ECC operation on the codeword at the first ECC protection level and the second ECC protection level. The codeword comprises payload data stored in a plurality of memory cells of the array, and parity data associated with the payload data stored in parity cells of the array.

Abstract: An insert for an electrical panel including an insulative block including a first edge, second edge, a pair of sides, a first end, and a second end. The insert further includes at least one void defined in the insulative block extending from the second edge into the insulative block.

Abstract: Steering light includes: providing, from a plurality of optical source ports, a respective optical wave that is tuned over different respective wavelengths, within different respective time slots; emitting at least a portion of the light from at least one optical phased array comprising a plurality of optical phase shifters, and a plurality of optical grating antennas; distributing at least a portion of the light using at least one optical distribution network (ODN) comprising: one or more ODN input ports, and two or more ODN output ports each coupled to a different respective one of the optical phase shifters; and coupling at least a portion of the light using at least one optical coupler (OC) comprising: at least one OC input port coupled to one of the optical source ports, and at least one OC output port coupled to one of the one or more ODN input ports.

Abstract: Systems and methods for fast multi-length payload error correcting includes at least a decoder circuit. The decoder circuit receives a first input and receives a second input. The decoder circuit generates, based on the first input, a first decoded payload. The first decoded payload includes at least a first data or a first length and a first flip bit. The decoder circuit generates, based on the second input, a second decoded payload. The second decoded payload includes at least a second data of a second length and a second flip bit, the second length being different from the first length.

Abstract: Methods, systems, and devices for bank-configurable power modes are described. Aspects include operating a memory device that has multiple memory banks in a first mode. While operating in the first mode, the memory device may receive a command to enter a second mode having a lower power consumption level than the first mode. The memory device may enter the second mode by switching a first subset of the memory banks to a first low power mode that operates at a first power consumption level and a second subset of the memory banks to a second low power mode that operates at a second power consumption level that may be lower than the first power consumption level. In some cases, the memory device may switch the first subset of memory banks from the first low power mode while maintaining the second subset of memory banks in the low power mode.

Abstract: Systems and methods for error location and error correction includes receiving, at a processor circuit, an input. The processor circuit generates a set of syndrome coefficients based on the input. The processor circuit generates a parity vector for the input based on the set of syndrome coefficients. The processor circuit determines a number of errors present in the input. Responsive to determining the number of errors present in the input, the processor circuit corrects the number of errors.

Abstract: In some implementations, the techniques described herein relate to a method including: receiving a codeword, the codeword having a first portion and a second portion, the first portion including user data and the second portion including synthesized data; detecting, using an ECC engine, at least one error in the codeword at a first position; and signaling an error misdetection when the first position is within the second portion.

Abstract: Methods, systems, and devices for shared decoder architecture for three-dimensional memory arrays are described. A memory device may include pillars coupled to an access line using two transistors positioned between the pillar and the access line. The gates of the two transistors may be coupled with respective gate lines coupled with circuitry configured to bias the gate line as part of an access operation for a memory cell coupled with the pillar. In some cases, the circuitry may be positioned between tiles of the memory device, at an end of one or more tiles of the memory device, between word line combs of a tile of the memory device, or a combination thereof.

Abstract: An apparatus includes: an optical phased array (e.g., on a photonic integrated circuit), a focusing element, which can be at a fixed position relative to the optical phased array and configured to receive an optical beam from the optical phased array, and a steering element, which can be at a fixed position relative to the focusing element and configured to transmit the optical beam received from the focusing element. In some implementations, at least one of the focusing element or the steering element is externally coupled to the photonic integrated circuit.

Abstract: A method to perform data scrub operations by operating a memory device, the memory device comprising a main memory, an internal Error Correction Code (ECC) engine and a scrub memory. The method comprising: receiving a read command; accessing, based on the receiving the read command, a location in the main memory to read data at the location; error correcting data read during the accessing; and storing at the scrub memory information of the location based at least in part on the correcting the data meeting or exceeding an ECC threshold.

Abstract: In some aspects, the techniques described herein relate to a method including: generating quantized Knuth (QK) index bits for a codeword, the QK index bits selected from a list of QK bits; computing a parity portion based on the payload and the QK index bits; combining the payload, parity portion, and the QK index bits to form a codeword; and writing the codeword to a memory device.

Abstract: In some aspects, the techniques described herein relate to a method including: receiving a standard error code correction (ECC) matrix, the standard ECC matrix including a portion for checking a payload and a portion for checking a parity of the payload; and extending the ECC matrix to form an extended matrix by adding a plurality of rows and a plurality of columns to form an upper matrix and a lower matrix, wherein the plurality of rows and columns include at least one all zero portion, at least one portion for checking a quantized Knuth (QK) index, and a portion for checking a parity of the QK index.