Abstract: A process for the in situ formation of a selective contact and a local interconnect on a semiconductor substrate. The exposed semiconductor substrate regions of a semiconductor device structure may be treated in a plasma to enhance the adhesiveness of a selective contact thereto. The semiconductor device structure is positioned within a reaction chamber, wherein a selective contact is deposited onto the exposed semiconductor substrate regions. Any residual selective contact material may be removed from oxide surfaces either intermediately or after selective contact deposition. While the semiconductor device remains in the reaction chamber, a local interconnect is deposited over the semiconductor device structure. The local interconnect may then be patterned. Subsequent layers may be deposited over the local interconnect. The present invention also includes semiconductor device structures formed by the inventive process.

Abstract: A method of forming trench isolation includes etching first trench lines into semiconductive material of a semiconductor substrate. First isolation material is formed within the first trench lines within the semiconductive material. After forming the first isolation material within the first trench lines, second trench lines are etched into semiconductive material of the substrate between the first trench lines such that the first trench lines and second trench lines alternate. Second isolation material is formed within the second trench lines within the semiconductive material. Alternate and additional aspects are contemplated.

Abstract: Some embodiments include methods of forming dielectric materials associated with semiconductor constructions. A semiconductor substrate surface having two different compositions may be exposed to a first silanol, then to organoaluminum to form a monolayer, and finally to a second silanol to form a dielectric material containing aluminum from the organoaluminum together with silicon and oxygen from the second silanol. Alternatively, or additionally, an organoaluminum monolayer may be formed across a semiconductor substrate, and then exposed to silanol within a deposition chamber, with the silanol being provided in two doses. Initially, a first dose of the silanol is injected the chamber, and then the first dose is flushed from the chamber to remove substantially all unreacted silanol from within the chamber. Subsequently, the second dose of silanol is injected into the chamber. Some embodiments include semiconductor constructions.

Abstract: A method of reducing the amount of halogenated materials in a halogen-containing environment. The method comprises introducing an aluminum compound into the halogen-containing environment, reacting the aluminum compound with the halogenated material to form a gaseous reaction product, and removing the gaseous reaction product from the environment. The aluminum compound may be a trialkylaluminum compound, an alane, an alkylaluminum hydride, an alkylaluminum halide, an alkylaluminum sesquihalide, or an aluminum sesquihalide. The aluminum compound may alternatively form a solid aluminum product, which is deposited on a surface associated with the halogen-containing environment or onto a semiconductor disposed therewithin. The halogenated material is incorporated into the solid aluminum product, forming an inert film within which the halogenated material is trapped.

Abstract: A method of forming trench isolation includes etching first trench lines into semiconductive material of a semiconductor substrate. First isolation material is formed within the first trench lines within the semiconductive material. After forming the first isolation material within the first trench lines, second trench lines are etched into semiconductive material of the substrate between the first trench lines such that the first trench lines and second trench lines alternate. Second isolation material is formed within the second trench lines within the semiconductive material. Alternate and additional aspects are contemplated.

Abstract: A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely spaced regions, such as a memory transistor array, and widely spaced regions, such as a periphery. Under conditions specified, the dielectric layer forms to have a first thickness over the closely spaced regions and a second thickness over the widely spaced regions. The second thickness is much thinner than the first thickness and dielectric over the widely spaced regions may be etched away with a blanket etch which leaves the majority of the dielectric layer over the closely spaced regions.

Abstract: Some embodiments include methods of forming dielectric materials associated with semiconductor constructions. A semiconductor substrate surface having two different compositions may be exposed to a first silanol, then to organoaluminum to form a monolayer, and finally to a second silanol to form a dielectric material containing aluminum from the organoaluminum together with silicon and oxygen from the second silanol. Alternatively, or additionally, an organoaluminum monolayer may be formed across a semiconductor substrate, and then exposed to silanol within a deposition chamber, with the silanol being provided in two doses. Initially, a first dose of the silanol is injected the chamber, and then the first dose is flushed from the chamber to remove substantially all unreacted silanol from within the chamber. Subsequently, the second dose of silanol is injected into the chamber. Some embodiments include semiconductor constructions.

Abstract: A storage capacitor plate for a semiconductor assembly comprising a substantially continuous porous conductive storage plate comprising silicon nanocrystals residing along a surface of a conductive material and along a surface of a coplanar insulative material adjacent the conductive material, a capacitor cell dielectric overlying the silicon nanocrystals and an overlying conductive top plate. The conductive storage plate is formed by a semiconductor fabrication method comprising forming silicon nanocrystals on a surface of a conductive material and on a surface of an insulative material adjacent the conductive material, wherein silicon nanocrystals contain conductive impurities and are adjoined to formed a substantially continuous porous conductive layer.

Abstract: A method of reducing the amount of halogenated materials in a halogen-containing environment. The method comprises introducing an aluminum compound into the halogen-containing environment, reacting the aluminum compound with the halogenated material to form a gaseous reaction product, and removing the gaseous reaction product from the environment. The aluminum compound may be a trialkylaluminum compound, an alane, an alkylaluminum hydride, an alkylaluminum halide, an alkylaluminum sesquihalide, or an aluminum sesquihalide. The aluminum compound may alternatively form a solid aluminum product, which is deposited on a surface associated with the halogen-containing environment or onto a semiconductor disposed therewithin. The halogenated material is incorporated into the solid aluminum product, forming an inert film within which the halogenated material is trapped.

Abstract: A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. Use of the process to produce layers, spacers, memory units, and gates is also disclosed, as well as the structures so produced.

Abstract: A process for enhanced selective deposition of a silicon oxide onto a substrate by pulsing delivery of the reactants through a linear injector is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. The ozone delivery is pulsed on and off. Optionally, the delivery of the ozone and the delivery of the TEOS are pulsed on and off alternately.

Abstract: A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely-spaced regions, such as a memory transistor array, and widely-spaced regions, such as a periphery. Under conditions specified, the dielectric layer forms to have a first thickness over the closely-spaced regions and a second thickness over the widely-spaced regions. The second thickness is much thinner than the first thickness and dielectric over the widely-spaced regions may be etched away with a blanket etch which leaves the majority of the dielectric layer over the closely-spaced regions.

Abstract: A storage capacitor plate for a semiconductor assembly having a substantially continuous porous conductive storage plate comprising silicon nanocrystals residing along a surface of a conductive material and along a surface of a coplanar insulative material adjacent the conductive material, a capacitor cell dielectric overlying the silicon nanocrystals and an overlying conductive top plate. The conductive storage plate is formed by a semiconductor fabrication method comprising forming silicon nanocrystals on a surface of a conductive material and on a surface of an insulative material adjacent the conductive material, wherein silicon nanocrystals contain conductive impurities and are adjoined to form a substantially continuous porous conductive layer.

Abstract: A storage capacitor plate for a semiconductor assembly comprising a substantially continuous porous conductive storage plate comprising silicon nanocrystals residing along a surface of a conductive material and along a surface of a coplanar insulative material adjacent the conductive material, a capacitor cell dielectric overlying the silicon nanocrystals and an overlying conductive top plate. The conductive storage plate is formed by a semiconductor fabrication method comprising forming silicon nanocrystals on a surface of a conductive material and on a surface of an insulative material adjacent the conductive material, wherein silicon nanocrystals contain conductive impurities and are adjoined to form a substantially continuous porous conductive layer.

Abstract: A storage capacitor plate for a semiconductor assembly comprising a substantially continuous porous conductive storage plate comprising silicon nanocrystals residing along a surface of a conductive material and along a surface of a coplanar insulative material adjacent the conductive material, a capacitor cell dielectric overlying the silicon nanocrystals and an overlying conductive top plate. The conductive storage plate is formed by a semiconductor fabrication method comprising forming silicon nanocrystals on a surface of a conductive material and on a surface of an insulative material adjacent the conductive material, wherein silicon nanocrystals contain conductive impurities and are adjoined to formed a substantially continuous porous conductive layer.

Abstract: A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely-spaced regions, such as a memory transistor array, and widely-spaced regions, such as a periphery. Under conditions specified, the dielectric layer forms to have a first thickness over the closely-spaced regions and a second thickness over the widely-spaced regions. The second thickness is much thinner than the first thickness and dielectric over the widely-spaced regions may be etched away with a blanket etch which leaves the majority of the dielectric layer over the closely-spaced regions.

Abstract: A storage capacitor plate for a semiconductor assembly comprising a substantially continuous porous conductive storage plate comprising silicon nanocrystals residing along a surface of a conductive material and along a surface of a coplanar insulative material adjacent the conductive material, a capacitor cell dielectric overlying the silicon nanocrystals and an overlying conductive top plate. The conductive storage plate is formed by a semiconductor fabrication method comprising forming silicon nanocrystals on a surface of a conductive material and on a surface of an insulative material adjacent the conductive material, wherein silicon nanocrystals contain conductive impurities and are adjoined to formed a substantially continuous porous conductive layer.

Abstract: A process for enhanced selective deposition of a silicon oxide onto a substrate by pulsing delivery of the reactants through a linear injector is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. The ozone delivery is pulsed on and off. Optionally, the delivery of the ozone and the delivery of the TEOS are pulsed on and off alternately.

Abstract: A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is described. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. Compared to the deposition rate on exposed regions on non-doped silicon, the silicon oxide deposits at a faster rate on exposed regions of P-type silicon and at a slower rate on exposed regions of N-type silicon.

Abstract: A process for enhanced selective deposition of a silicon oxide onto a substrate by pulsing delivery of the reactants through a linear injector is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. The ozone delivery is pulsed on and off. Optionally, the delivery of the ozone and the delivery of the TEOS are pulsed on and off alternately.