Abstract: To minimize the voltage drops in an electronic circuit, existing instances are moved and decoupling capacitors are automatically inserted according to an algorithm. A model of the voltage drop on a row of gate elements is presented. The model allows for rapid computations of the effect of a particular move or insertion on voltage drop in the circuit.

Abstract: To minimize the voltage drops in an electronic circuit, existing instances are moved and decoupling capacitors are automatically inserted according to an algorithm. A model of the voltage drop on a row of gate elements is presented. The model allows for rapid computations of the effect of a particular move or insertion on voltage drop in the circuit.

Abstract: A D/A converter having a feedback capacitor C1 between the inverting input and output of an operational amplifier A1 having a virtual ground on the inverting input. First switch means is sequentially responsive to binary values of bits of a digital input word for connecting a bus line to either a reference voltage or ground. Second switch means alternately connects opposite sides of a second capacitor C2.dbd.C1 between ground and the bus line for sampling the logic level of a bit, and across C1 for redistributing sampled charge during each bit. The charge on C1 is transferred to a storage capacitor and then reset to zero at the end of each word. In an alternate embodiment, one of a pair of switched capacitors samples the logic level while the other is connected across C1 for redistributing stored charge. In another embodiment, binary weighted capacitors sample the logic levels of bits in pairs and are simultaneously connected across C1 for redistributing charge.

Abstract: A D/A converter having a feedback capacitor C1 between the inverting input and output of an operational amplifier A1 having a virtual ground on the inverting input. First switch means is sequentially responsive to binary values of bits of a digital input word for connecting a bus line to either a reference voltage or ground. Second switch means alternately connects opposite sides of a second capacitor C2=C1 between ground and the bus line for sampling the logic level of a bit, and across C1 for redistributing sampled charge during each bit. The charge on C1 is transferred to a storage capacitor and then reset to zero at the end of each word. In an alternate embodiment, one of a pair of switched capacitors samples the logic level while the other is connected across C1 for redistributing stored charge. In another embodiment, binary weighted capacitors sample the logic levels of bits in pairs and are simultaneously connected across C1 for redistributing charge.

Abstract: An integratable mu-law PCM decoder including only a single operational amplifier having a unit valued feedback capacitor C1, and second and third unit valued switched capacitors C2 and C3. Switch means cyclically connects C2 between ground and either ground or a reference voltage, and across C1 for providing an indication on C2 of the step offset in a prescribed segment; cyclically connects C3 between ground and the reference voltage and across C1 for stepping through segments below the prescribed segments; transfers all of the charge on C2 to C1 for the prescribed segment; and alternately connects opposite sides of C3 to ground and across C1 for segments above the prescribed segment for redistributing charge on the capacitors and producing an analog signal sample on C1. In an alternate embodiment for satisfying the A-law, all charge on C3 is transferred to C1 for only a first segment that is below the prescribed segment.

Abstract: A pair of fixed capacitors are connected across a pair of serially coupled switched capacitors, the junction of the fixed capacitors being coupled to the floating node of the switched capacitors. As the polarities of the switched capacitors are switched, the fixed capacitors cause a partial discharge, thereby preventing charge from accumulating on the node.

Abstract: An integratable mu-law PCM decoder including only a single operational amplifier having a unit valued feedback capacitor C1, and second and third unit valued switched capacitors C2 and C3. Switch means cyclically connects C2 between ground and either ground or a reference voltage, and across C1 for providing an indication on C2 of the step offset in a prescribed segment; cyclically connects C3 between ground and the reference voltage and across C1 for stepping through segments below the prescribed segments; transfers all of the charge on C2 to C1 for the prescribed segment; and alternately connects opposite sides of C3 to ground and across C1 for segments above the prescribed segment for redistributing charge on the capacitors and producing an analog signal sample on C1. In an alternate embodiment for satisfying the A-law, all charge on C3 is transferred to C1 for only a first segment that is below the prescribed segment.

Abstract: An integratable PCM decoder requiring a total capacitance of only 32 times the normalized capacitance Co of the smallest capacitor thereof. The decoder comprises a source of positive and negative reference voltages, a differential input operational amplifier having its non-inverting input connected to ground, a storage capacitor CO=16Co connected as a feedback capacitor between the inverting input and the output terminals of the amplifier so that they operate as a voltage source, binary weighted capacitors C1=Co, C2=Co, C3=4Co and C4=8Co, and a second unit weighted capacitor C5=Co. In a mu-law decoder, switch means alternately connect one and other sides of ones of C1-C5 (1) between ground and either a.+-.reference voltage or ground, in accordance with the characterizations in a PCM coded digital input word, and (2) across the storage capacitor CO for redistributing charge on the capacitors for each segment of a designated polarity.

Abstract: An integratable PCM decoder that is relatively insensitive to parasitic and stray capacitance effects and that requires a total capacitance of only 32 times the normalized capacitance Co of the smallest capacitor thereof. The decoder comprises a source of positive and negative reference voltages; a differential input operational amplifier having its non-inverting input connected to ground; a storage capacitor CO=16Co connected as a feedback capacitor between the inverting input and the output terminals of the amplifier so that they operate as a voltage source; binary weighted capacitors C1=Co, C2=2Co, C3=4Co and C4=8Co; and a second unit weighted capacitor C5=Co. In an a-law decoder, switch means alternately connects one and other sides of ones of C1-C5 (1) between ground and either a.+-.

Abstract: A D/A converter having a feedback capacitor C1 between the inverting input and output of an operational amplifier A1 having a virtual ground on the inverting input. First switch means is sequentially responsive to binary values of bits of a digital input word for connecting a bus line to either a reference voltage or ground. Second switch means alternately connects opposite sides of a second capacitor C2=C1 between ground and the bus line for sampling the logic level of a bit, and across C1 for redistributing sampled charge during each bit. The charge on C1 is transferred to a storage capacitor and then reset to zero at the end of each word. In an alternate embodiment, one of a pair of switched capacitors samples the logic level while the other is connected across C1 for redistributing stored charge. In another embodiment, binary weighted capacitors sample the logic levels of bits in pairs and are simultaneously connected across C1 for redistributing charge.

Abstract: Multiplexor with internal decoding. Signal levels at two select input terminals select the data input at one of four data input terminals to be applied to an output terminal. The multiplexor includes three sets of pairs of transistors connected in a series arrangement. In one embodiment the current source for the transistors includes a resistance and diode in parallel connected between ground and the transistors of the third set and a resistance connected between a source of negative potential and the transistors of the first set. In another embodiment the current source includes a dual emitter transistor biased to operate as a constant current source connected between the source of negative potential and the transistors of the first set in place of the resistance.

Abstract: A system includes arithmetic logic units, each including two 2:1 multiplexers, one 8:1 multiplexer, and a three input majority gate. Each 2:1 multiplexer provides a specific one of two data inputs when a select input signal is at a specific one of two binary states. The 8:1 multiplexer provides output signals indicative of specific ones of eight data inputs in accordance with the binary states of three select input signals. Electrical signals indicative of two input variables are coupled, respectively, to the select input of the two 2:1 multiplexers. Two outputs therefrom are coupled to two of three select inputs of the 8:1 multiplexer, and to two inputs of the majority gate.A carry-in signal is coupled to both the third select input of the 8:1 multiplexer, and to the third input of the majority gate. The arithmetic logic unit acts as an adder, subtractor, AND gate, OR circuit, exclusive OR circuit, and NOR circuit.Arithmetic and logical functions on two input binary variables of the form A.sub.0, A.sub.1. .