Patents by Inventor Christopher W. Kunce

Christopher W. Kunce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for providing adjustable latency for test mode compression
    Patent number: 7139943
    Abstract: An integrated circuit includes a core memory array and a test mode compression circuit. The test mode compression circuit receives test mode data from the core memory array. A multiplexer receives read data from the core memory array and test mode data from the test mode compression circuit. The multiplexer receives a test mode compression signal and selectively transfers one of the read data and the test mode data dependent at least in part upon the test mode compression signal.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: November 21, 2006
    Assignee: Infineon Technologies AG
    Inventors: Torsten Partsch, Biju Velayudhan, Christopher W. Kunce
  • System of multiplexed data lines in a dynamic random access memory
    Patent number: 7088624
    Abstract: A system of multiplexed data lines in a DRAM integrated circuit includes a switching circuit having two switching states. In one switching state, the data lines connect to a first configuration of data paths as would occur in a typical DRAM integrated circuit. A limited number of spare column select lines are available to repair defective column select lines in the first configuration. In another switching state, the data lines connect to a second configuration of the data paths, doubling the number of spare column select lines available to repair a defective column select line.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: August 8, 2006
    Assignee: Infineon Technologies, A.G.
    Inventors: Alan Daniel, Christopher W. Kunce
  • Method and apparatus for providing adjustable latency for test mode compression
    Publication number: 20030188238
    Abstract: An integrated circuit includes a core memory array and a test mode compression circuit. The test mode compression circuit receives test mode data from the core memory array. A multiplexer receives read data from the core memory array and test mode data from the test mode compression circuit. The multiplexer receives a test mode compression signal and selectively transfers one of the read data and the test mode data dependent at least in part upon the test mode compression signal.
    Type: Application
    Filed: March 29, 2002
    Publication date: October 2, 2003
    Applicant: Infineon Technologies North America Corp.
    Inventors: Torsten Partsch, Biju Velayudhan, Christopher W. Kunce