Abstract: Systems and methods are disclosed that provide smart alerts to users, e.g., alerts to users about diabetic states that are only provided when it makes sense to do so, e.g., when the system can predict or estimate that the user is not already cognitively aware of their current condition, e.g., particularly where the current condition is a diabetic state warranting attention. In this way, the alert or alarm is personalized and made particularly effective for that user. Such systems and methods still alert the user when action is necessary, e.g., a bolus or temporary basal rate change, or provide a response to a missed bolus or a need for correction, but do not alert when action is unnecessary, e.g., if the user is already estimated or predicted to be cognitively aware of the diabetic state warranting attention, or if corrective action was already taken.

Abstract: A transmitter for a chaos communications system employing chaotic symbol modulation that perform auto-indexing, temporal gain control, increased path diversity and sequence lock up prevention. The transmitter includes a symbol mapper that converts a series of information bits to a series of bit symbols, and a chaos modulator providing chaotic spreading modulation of the bit symbols. The chaos modulator includes a plurality of chaos generators, one for each bit symbol, providing a chaos sequence for the bit symbols. Each chaos modulator includes a RAM/ROM that provides auto-indexing where a chaos sequence output from the RAM/ROM is fed back to an input of the RAM/ROM from which a chaos sequence at a next address in the RAM/ROM is selected as the output of the modulator.

Abstract: A transmitter for a chaos communications system employing chaotic symbol modulation that perform auto-indexing, temporal gain control, increased path diversity and sequence lock up prevention. The transmitter includes a symbol mapper that converts a series of information bits to a series of bit symbols, and a chaos modulator providing chaotic spreading modulation of the bit symbols. The chaos modulator includes a plurality of chaos generators, one for each bit symbol, providing a chaos sequence for the bit symbols. Each chaos modulator includes a RAM/ROM that provides auto-indexing where a chaos sequence output from the RAM/ROM is fed back to an input of the RAM/ROM from which a chaos sequence at a next address in the RAM/ROM is selected as the output of the modulator.

Abstract: A communications system that pseudo-randomly dithers the widths of chips that are multiplied by bit symbols for spread spectrum purposes. The system includes a first random sequence generator that generates a first sequence of random numbers at a sample rate and a decision processor responsive to the first sequence of random numbers that generates a separate command at the sample rate each time one of the random numbers exceeds a predetermined threshold. The system further includes a second random sequence generator that generates select random numbers, where the second random number generator changes the select random number each time it receives one of the commands. The system also includes a chip width processor responsive to the random numbers from the second random sequence generator, where the chip width processor selects a new set of chips each having a certain width in response to receiving each random number.

Abstract: A sub-sampling system that is part of a modulator in a transmitter employing a chaos based architecture and including a symbol mapper and a chaos generator. The system includes M-number of channels each receiving a sequence of chaos samples from the generator and a delay device in all of the channels except one that delay the chaos samples at different delay times. The system also includes a sub-sampler in all of the channels that receive the delayed samples, where each sub-sampler outputs every predetermined one of the chaos samples and a register in each channel each storing a predetermined number of the sub-sampled chaos samples. A selection switch responsive to the stored sub-sampled chaos samples from the registers, where the selection switch is responsive to a selection signal from the symbol mapper that selects one of the registers to output the sequences of stored sub-sampled chaos samples from the system.

Abstract: A method and system of symbol measurement and combining (SMaC) provides near-optimal performance for each user independently by relying on rapid digital beamforming with near-ideal convergence properties. This approach is also provides near-ideal performance without any knowledge of user/jammer location and adapts instantly as those locations change. An iterative joint estimation method is used to determine a covariance matrix RXX, and a user beamsteering vector, ?.

Abstract: One example includes a rate detector system. The rate detector system includes a plurality of energy detectors configured to receive an input signal and to filter separate respective frequency bands associated with the input signal to generate separate respective energy profiles. The system also includes an energy processing component configured to determine a symbol rate of the input signal based on a statistical evaluation of a ratio of the separate respective energy profiles.

Abstract: One example includes a rate detector system. The rate detector system includes a plurality of energy detectors configured to receive an input signal and to filter separate respective frequency bands associated with the input signal to generate separate respective energy profiles. The system also includes an energy processing component configured to determine a symbol rate of the input signal based on a statistical evaluation of a ratio of the separate respective energy profiles.

Abstract: A decoder of a data signal subjected to phase shifting keying (PSK) modulation uses a plurality of phase locked loops (801-1 to 801-n) having an inner decoder for short block codes, at least one of which is adapted to apply excess processing power to process a selected burst of the data signal, such as processing the burst with multiple initial phase/frequency error estimates. A selection circuit identifies the burst and supplies to said one of said plurality of phase-locked loops (801-1 to 801-n) for re-processing the bust with excess processing power. An outer Reed-Solomon block decoder (319) may be used to correct errors in the codewords from the phase locked loops and may be used in the selection of the burst by the selection circuit.

Abstract: Constellations (22) arranged in a concentric circle pattern provide simplified control of modulated communication. A plurality of concentric circles (26, 28, 30) with defined points (24) include convolutionally coded and uncoded bits. Constellation patterns having three or four concentric circles (26, 28, 30) are provided. A magnitude error for each of the points (24) allows for deviations during communication. The constellations (22) provide efficient communication using non-linear channels.

Abstract: A decision directed phase locked loop (DD-PLL) is efficiently implemented in a communication receiver. The phase locked loop includes an enhanced block decoder inside a phase detector which takes in the baseband complex samples and the current channel phase estimate (or the tracked phase) and generates a feedback phase error term. A loop filter filters the phase error terms and a phase accumulator updates the tracked phase estimate on each iteration of the loop.

Abstract: A demodulator demodulates a modulated signal waveform in a data communication system. A phase tracking loop tracks the phase of said modulated signal waveform and having an inner block decoder configured to decode a set of vector pairs of the modulated signal waveform at a decode rate to generate associated codewords and phase estimates. A group of data symbols consisting of the first data symbols of the modulated signal waveform are run backwards through the phase tracking loop. An outer block decoder receives the associated codewords generated by said inner block decoder and utilizes and corrects only codewords associated with symbols after and including the group of data symbols consisting of the first data symbols of the modulated signal waveform.

Abstract: A decoder of a data signal subjected to phase shifting keying (PSK) modulation uses an inner decoder for short block codes within a phase locked loop which is adapted to process the data signal with multiple initial phase/frequency error estimates and to output sets of codewords and phase/frequency error estimates respectively corresponding to the initial phase/frequency estimates. A selection circuit (720) selects and forwards the output corresponding to one of the multiple phase/frequency estimates. An outer Reed-Solomon block decoder (319) corrects errors in the codewords from the set of associated codewords selected by the selection circuit.

Abstract: A demodulator for demodulating a QPSK modulated signal waveform in a data communication system, has a phase tracking loop tracking the phase of said QPSK modulated signal waveform and having an inner block decoder configured to decode a set of vector pairs of the modulated signal waveform at a decode rate to generate associated codewords and phase estimates. A group of data symbols consisting of the first data symbols of the QPSK modulated signal waveform are stored until a future waveform is received and then run backwards through the phase tracking loop concurrently with the data from the future waveform. An outer block decoder receives the associated codewords generated by said inner block decoder and utilizes and corrects only codewords associated with symbols after and including the group of data symbols consisting of the first data symbols of the QPSK modulated signal waveform.

Abstract: A demodulator demodulates a modulated signal waveform in a data communication system. A phase tracking loop tracks the phase of said modulated signal waveform and having an inner block decoder configured to decode a set of vector pairs of the modulated signal waveform at a decode rate to generate associated codewords and phase estimates. A group of data symbols consisting of the first data symbols of the modulated signal waveform are run backwards through the phase tracking loop. An outer block decoder receives the associated codewords generated by said inner block decoder and utilizes and corrects only codewords associated with symbols after and including the group of data symbols consisting of the first data symbols of the modulated signal waveform.

Abstract: A decoder of a data signal subjected to phase shifting keying (PSK) modulation uses a plurality of phase locked loops (801-1 to 801-n) having an inner decoder for short block codes, at least one of which is adapted to apply excess processing power to process a selected burst of the data signal, such as processing the burst with multiple initial phase/frequency error estimates. A selection circuit identifies the burst and supplies to said one of said plurality of phase-locked loops (801-1 to 801-n) for re-processing the bust with excess processing power. An outer Reed-Solomon block decoder (319) may be used to correct errors in the codewords from the phase locked loops and may be used in the selection of the burst by the selection circuit.

Abstract: A decoder of a data signal subjected to phase shifting keying (PSK) modulation uses an inner decoder for short block codes within a phase locked loop which is adapted to process the data signal with multiple initial phase/frequency error estimates and to output sets of codewords and phase/frequency error estimates respectively corresponding to the initial phase/frequency estimates. A selection circuit (720) selects and forwards the output corresponding to one of the multiple phase/frequency estimates. An outer Reed-Solomon block decoder corrects errors in the codewords from the set of associated codewords selected by the selection circuit. The Reed-Solomon block decoder corrects a combination of random errors and erasure errors where the erasure errors are chosen based on reliability metrics generated by the inner code or else the first positions of the data bursts are chosen for erasures as these are most likely to be in error relative to other positions.

Abstract: A decision directed phase locked loop (DD-PLL) is efficiently implemented in a communication receiver. The phase locked loop includes an enhanced block decoder inside a phase detector which takes in the baseband complex samples and the current channel phase estimate (or the tracked phase) and generates a feedback phase error term. A loop filter filters the phase error terms and a phase accumulator updates the tracked phase estimate on each iteration of the loop.

Abstract: Constellations (22) arranged in a concentric circle pattern provide simplified control of modulated communication. A plurality of concentric circles (26, 28, 30) with defined points (24) include convolutionally coded and uncoded bits. Constellation patterns having three or four concentric circles (26, 28, 30) are provided. A magnitude error for each of the points (24) allows for deviations during communication. The constellations (22) provide efficient communication using non-linear channels.

Abstract: An automatic force generating and control system including a lever pivotally attached to a monolith and a lower body exerciser pivotally attached to a bench, with both the bench and monolith attached to a platform. The rotation of the lower body exerciser is translated into linear movement by a series of sprockets and timing belts. The electrical output from load cells and potentiometers are processed by the electronic controls to determine the speed, direction and position and the amount and direction of force being exerted on the lever and lower body exerciser. Resistance to movement is provided by a lever hydraulics assembly and a lower body hydraulics assembly. The lever has arms and handles which articulate to the physique of the user and the exercise to be performed. The arms pivot in mirror relationship and the lower body exerciser may be lengthened or shortened. Electric solenoid clutches or hydraulics may engage the handles to the arms and the arms to the head of the lever.