Patents by Inventor Christopher Wade Ackerman

Christopher Wade Ackerman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240068572
    Abstract: The present disclosure is directed to a system having a first loading component and a second loading component for applying load to a device during a test of the device, the first loading component is configured to be moveable with respect to the second loading component. The system includes a seal member arranged between the first loading component and the second loading component, the seal member is adapted to engage the device diming testing so as to apply a load against the device during testing and provide sealing around a cavity positioned below the first loading component and above the device.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Paul DIGLIO, Craig YOST, Christopher Wade ACKERMAN
  • Patent number: 11808813
    Abstract: An apparatus includes a processor configured to control an automatic test equipment (ATE) to measure one or more parameters of a current test instance for testing a device under test (DUT), during execution of the current test instance on the DUT, and determine, based on the measured one or more parameters, one or more controls for controlling a temperature of a thermal head connected to the DUT so that a junction temperature of the DUT corresponds to a predetermined test temperature. The processor is further configured to control the temperature of the thermal head, based on the determined one or more controls.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: November 7, 2023
    Assignee: Intel Corporation
    Inventors: Mahesh Deshmane, Shoujie He, Christopher Wade Ackerman, Jacob Hales, Johnny Mata Vega, Joseph Zearing
  • Publication number: 20230288480
    Abstract: An apparatus includes a processor configured to control an automatic test equipment (ATE) to measure one or more parameters of a current test instance for testing a device under test (DUT), during execution of the current test instance on the DUT, and determine, based on the measured one or more parameters, one or more controls for controlling a temperature of a thermal head connected to the DUT so that a junction temperature of the DUT corresponds to a predetermined test temperature. The processor is further configured to control the temperature of the thermal head, based on the determined one or more controls.
    Type: Application
    Filed: March 11, 2022
    Publication date: September 14, 2023
    Inventors: Mahesh DESHMANE, Shoujie HE, Christopher Wade ACKERMAN, Jacob HALES, Johnny MATA VEGA, Joseph ZEARING
  • Patent number: 11464139
    Abstract: A conformable heat sink interface for an integrated circuit package comprises a mounting plate having a first surface and a deformable membrane having a portion bonded to a second surface of the plate. A cavity is between the second surface of the plate and the deformable membrane. A flowable heat transfer medium is within the cavity. The flowable heat transfer medium has a thermal conductivity of not less than 30 W/m K. The deformable membrane is to conform to a three-dimensional shape of an IC package and the mounting plate has a second surface that is to be adjacent to a heat sink base.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: October 4, 2022
    Assignee: Intel Corporation
    Inventors: Kelly Lofgreen, Joseph Petrini, Todd Coons, Christopher Wade Ackerman, Edvin Cetegen, Yang Jiao, Michael Rutigliano, Kuang Liu
  • Patent number: 11032941
    Abstract: Systems, apparatuses, methods, and computer-readable media are presented for managing an apparatus for thermal energy management including a first container. The first container includes a first cavity, and is configured to hold a first liquid coolant within the first cavity to at least partially surround a second container. The second container includes a second cavity configured to hold one or more heat sources, and a second liquid coolant to at least partially surround the one or more heat sources. The second container is sealed to separate the first liquid coolant from the second liquid coolant. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Minh Le, Thomas Boyd, Bijoyraj Sahu, Evan Chenelly, Christopher Wade Ackerman, Carlos Alvizo Flores, Craig Jahne
  • Publication number: 20200146183
    Abstract: A conformable heat sink interface for an integrated circuit package comprises a mounting plate having a first surface and a deformable membrane having a portion bonded to a second surface of the plate. A cavity is between the second surface of the plate and the deformable membrane. A flowable heat transfer medium is within the cavity. The flowable heat transfer medium has a thermal conductivity of not less than 30 W/m K. The deformable membrane is to conform to a three-dimensional shape of an IC package and the mounting plate has a second surface that is to be adjacent to a heat sink base.
    Type: Application
    Filed: November 5, 2018
    Publication date: May 7, 2020
    Applicant: Intel Corporation
    Inventors: Kelly Lofgreen, Joseph Petrini, Todd Coons, Christopher Wade Ackerman, Edvin Cetegen, Yang Jiao, Michael Rutigliano, Kuang Liu
  • Publication number: 20190223324
    Abstract: Systems, apparatuses, methods, and computer-readable media are presented for managing an apparatus for thermal energy management including a first container. The first container includes a first cavity, and is configured to hold a first liquid coolant within the first cavity to at least partially surround a second container. The second container includes a second cavity configured to hold one or more heat sources, and a second liquid coolant to at least partially surround the one or more heat sources. The second container is sealed to separate the first liquid coolant from the second liquid coolant. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 28, 2019
    Publication date: July 18, 2019
    Inventors: Minh Le, Thomas Boyd, Bijoyraj Sahu, Evan Chenelly, Christopher Wade Ackerman, Carlos Alvizo Flores, Craig Jahne
  • Patent number: 10281521
    Abstract: Techniques for thermal management of a device under test are discussed. In an example, an apparatus may include a pedestal having a device-specific surface configured to exchange heat with the integrated circuit while the device-specific surface is in contact with a surface of the integrated circuit or separated from the surface of the integrated circuit by a layer of thermally conductive material, and a heat generating element configured to heat the device-specific surface. In certain examples, the pedestal may include a plurality of channels configured to couple to a manifold and to route thermal material from the manifold through an interior of the pedestal for maintaining temperature control of the surface of an integrated circuit under test.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: David Won-jun Song, James R. Hastings, Akhilesh P. Rallabandi, Morten S. Jensen, Christopher Wade Ackerman, Christopher R. Schroeder, Nader N. Abazarnia, John C. Johnson
  • Publication number: 20180156863
    Abstract: Techniques for thermal management of a device under test are discussed. In an example, an apparatus may include a pedestal having a device-specific surface configured to exchange heat with the integrated circuit while the device-specific surface is in contact with a surface of the integrated circuit or separated from the surface of the integrated circuit by a layer of thermally conductive material, and a heat generating element configured to heat the device-specific surface. In certain examples, the pedestal may include a plurality of channels configured to couple to a manifold and to route thermal material from the manifold through an interior of the pedestal for maintaining temperature control of the surface of an integrated circuit under test.
    Type: Application
    Filed: December 2, 2016
    Publication date: June 7, 2018
    Inventors: David Won-jun Song, James R. Hastings, Akhilesh P. Rallabandi, Morten S. Jensen, Christopher Wade Ackerman, Christopher R. Schroeder, Nader N. Abazarnia, John C. Johnson
  • Patent number: 7701238
    Abstract: In one embodiment, the present invention includes a burn-socket for insertion into a test board, where the burn-in socket is coupled to receive a semiconductor device under test (DUT). The burn-in socket includes a substrate to support the semiconductor DUT, which includes a heating element embedded in a layer of the substrate. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Anthony Yeh Chiing Wong, Victor Henckel, Boon Liang Heng, Christopher Wade Ackerman, James C. Shipley
  • Publication number: 20090002010
    Abstract: In one embodiment, the present invention includes a burn-socket for insertion into a test board, where the burn-in socket is coupled to receive a semiconductor device under test (DUT). The burn-in socket includes a substrate to support the semiconductor DUT, which includes a heating element embedded in a layer of the substrate. Other embodiments are described and claimed.
    Type: Application
    Filed: June 26, 2007
    Publication date: January 1, 2009
    Inventors: Anthony Yeh Chiing Wong, Victor Henckel, Boon Liang Heng, Christopher Wade Ackerman, James C. Shipley
  • Publication number: 20080302783
    Abstract: In one embodiment, a test board includes a plurality of socket locations each to receive a corresponding burn-in socket which in turn is to receive a semiconductor device under test (DUT). Each of the socket locations includes a heating element embedded within the test board, which may be used to provide thermal conduction to the DUT during a burn-in test. Other embodiments are described and claimed.
    Type: Application
    Filed: June 8, 2007
    Publication date: December 11, 2008
    Inventors: Anthony Yeh Chiing Wong, Christopher Wade Ackerman, James C. Shipley, Hon Lee Kon