Patents by Inventor Christopher Wilkerson

Christopher Wilkerson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210214092
    Abstract: Airbags for use in aircraft and other vehicles are described herein. In some embodiments, an airbag can deploy from a structure forward of a seated occupant at a generally upward angle relative to a longitudinal axis of the aircraft. The distal end portion of the airbag can include a recessed impact surface portion configured to receive the head and/or neck of the seat occupant.
    Type: Application
    Filed: January 9, 2020
    Publication date: July 15, 2021
    Inventors: Hyunsok Pang, James Christopher Wilkerson
  • Publication number: 20200081718
    Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 12, 2020
    Inventors: Christopher Wilkerson, Binh Pham, Patrick Lu, Jared Warner Stark, IV
  • Patent number: 10528473
    Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: January 7, 2020
    Assignee: Intel Corporation
    Inventors: Christopher Wilkerson, Muhammad M. Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
  • Patent number: 10521236
    Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventors: Christopher Wilkerson, Binh Pham, Patrick Lu, Jared Warner Stark, IV
  • Publication number: 20190303162
    Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Inventors: Christopher Wilkerson, Binh Pham, Patrick Lu, Jared Warner Stark, IV
  • Publication number: 20180373632
    Abstract: An apparatus and method are described for a triggered prefetch operation. For example, one embodiment of a processor comprises: a first core comprising a first cache to store a first set of cache lines; a second core comprising a second cache to store a second set of cache lines; a cache management circuit to maintain coherency between one or more cache lines in the first cache and the second cache, the cache management circuit to allocate a lock on a first cache line to the first cache; a prefetch circuit comprising a prefetch request buffer to store a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line, the prefetch circuit to cause the first cache line to be prefetched to the second cache in response to an invalidate command detected for the first cache line.
    Type: Application
    Filed: August 6, 2018
    Publication date: December 27, 2018
    Inventors: Christopher WILKERSON, Ren WANG, Antoine KAUFMANN, Anil VASUDEVAN, Robert G. BLANKENSHIP, Venkata KRISHNAN, Tsung-Yuan C. Tai
  • Publication number: 20180060239
    Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
    Type: Application
    Filed: June 13, 2017
    Publication date: March 1, 2018
    Inventors: CHRISTOPHER WILKERSON, MUHAMMAD M. KHELLAH, VIVEK DE, MING ZHANG, JAUME ABELLA, JAVIER CARRETERO CASADO, PEDRO CHAPARRO MONFERRER, XAVIER VERA, ANTONIO GONZALEZ
  • Patent number: 9710391
    Abstract: Various embodiments of the invention concern methods and apparatuses for power and time efficient load handling. A compiler may identify producer loads, consumer reuse loads, consumer forwarded loads, and producer/consumer hybrid loads. Based on this identification, performance of the load may be efficiently directed to a load value buffer, store buffer, data cache, or elsewhere. Consequently, accesses to cache are reduced, through direct loading from load value buffers and store buffers, thereby efficiently processing the loads.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: Wei Liu, Youfeng Wu, Christopher Wilkerson, Herbert Hum
  • Patent number: 9678878
    Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: June 13, 2017
    Assignee: Intel Corporation
    Inventors: Christopher Wilkerson, Muhammad M. Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
  • Patent number: 9229872
    Abstract: A method is described that includes during runtime of a semiconductor die, determining that a next BIST test sequence of a storage component embedded on the die is appropriate. The method further includes applying a BIST test sequence to each valid entry in the storage component. The method also includes marking any newly invalid entries in the storage component as invalid and configuring a respective replacement entry for each of the newly invalid entries.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 5, 2016
    Assignee: Intel Corporation
    Inventors: Christopher Wilkerson, Jawad Nasrullah, Kelvin Kwan
  • Patent number: 8868836
    Abstract: Methods and apparatus to reduce minimum operating voltage through a hybrid cache design are described. In one embodiment, a cache with different size bit cells may be used, e.g., to reduce minimum operating voltage of an integrated circuit device that includes the cache and possibly other logic (such as a processor). Other embodiments are also described.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: October 21, 2014
    Assignee: Intel Corporation
    Inventors: Muhammad M. Khellah, Christopher Wilkerson, Alaa R. Alameldeen, Bibiche M. Geuskens, Tanay Karnik, Vivek De, Gunjan H. Pandya
  • Publication number: 20140281254
    Abstract: A method is described that includes during runtime of a semiconductor die, determining that a next BIST test sequence of a storage component embedded on the die is appropriate. The method further includes applying a BIST test sequence to each valid entry in the storage component. The method also includes marking any newly invalid entries in the storage component as invalid and configuring a respective replacement entry for each of the newly invalid entries.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Christopher WILKERSON, Jawad NASRULLAH, Kelvin KWAN
  • Publication number: 20140108733
    Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
    Type: Application
    Filed: October 16, 2012
    Publication date: April 17, 2014
    Inventors: Christopher Wilkerson, Muhammad M. Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
  • Publication number: 20130246712
    Abstract: Various embodiments of the invention concern methods and apparatuses for power and time efficient load handling. A compiler may identify producer loads, consumer reuse loads, consumer forwarded loads, and producer/consumer hybrid loads. Based on this identification, performance of the load may be efficiently directed to a load value buffer, store buffer, data cache, or elsewhere. Consequently, accesses to cache are reduced, through direct loading from load value buffers and store buffers, thereby efficiently processing the loads.
    Type: Application
    Filed: May 3, 2013
    Publication date: September 19, 2013
    Inventors: WEI LIU, YOUFENG WU, CHRISTOPHER WILKERSON, HERBERT HUM
  • Patent number: 8291168
    Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 31, 2011
    Date of Patent: October 16, 2012
    Assignee: Intel Corporation
    Inventors: Christopher Wilkerson, Muhammad M. Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
  • Publication number: 20120110266
    Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
    Type: Application
    Filed: December 31, 2011
    Publication date: May 3, 2012
    Inventors: Christopher Wilkerson, M. Muhammad Khellah, Vivek De, Ming Y. Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
  • Patent number: 8103830
    Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: January 24, 2012
    Assignee: Intel Corporation
    Inventors: Christopher Wilkerson, Muhammad M. Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
  • Publication number: 20100257529
    Abstract: With some embodiments, task processing based on power availability is provided for mobile computing platforms including laptops, tablets, netbooks, cell phones, as well as for other devices or systems that are not mobile such as desktop computers and server systems.
    Type: Application
    Filed: April 6, 2009
    Publication date: October 7, 2010
    Inventors: Christopher Wilkerson, Ming Zhang, Wei Wu
  • Publication number: 20100082905
    Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventors: Christopher Wilkerson, Muhammad M. Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
  • Publication number: 20090172283
    Abstract: Methods and apparatus to reduce minimum operating voltage through a hybrid cache design are described. In one embodiment, a cache with different size bit cells may be used, e.g., to reduce minimum operating voltage of an integrated circuit device that includes the cache and possibly other logic (such as a processor). Other embodiments are also described.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventors: Muhammad M. Khellah, Christopher Wilkerson, Alaa R. Alameldeen, Bibiche M. Geuskens, Tanay Karnik, Vivek De, Gunjan H. Pandya