Abstract: A buffer is disclosed for storing data being transferred using a plurality of control channels, a data item of said data being transferred between a data source and a data destination using one of said plurality of control channels, said buffer comprising: a data input port operable to receive said data being transferred using said plurality of control channels; a data output port operable to output data to be transferred using said plurality of control channels; and a data store operable to store data received from said data input port prior to it being output by said data output port, said data store comprising a plurality of storage locations each operable to store a data item, said storage locations being arranged in groups, a storage location being allocated to a group in dependence on the control channel that a data item that it stores is received from, such that each group comprises storage locations storing data items received from a same one of said plurality of control channels.

Abstract: The application discloses a direct memory access controller operable to control data transfer between a plurality of data source and data destination pairs comprising: at least one port operable to receive data from at least one data source and to output data to at least one data destination; and a channel operable to transfer data between said at least some of said plurality of data source and data destination pairs, said channel comprising registers operable to store data transfer control data, said data transfer control data comprising a source address of said data to be transferred, a destination address of said data to be transferred and control data, said data source address and said data destination address specifying said data source and data destination; wherein prior to a data transfer between a data source and data destination pair said direct memory access controller is operable to request data transfer control data corresponding to said data source and data destination pair from a memory and to s

Abstract: A data processing apparatus comprising a plurality of data processors, each data processor comprising: first logic operable in a first clock domain and further logic operable in a second clock domain, said first and second clock domains being asynchronous with each other; a synchroniser operable to synchronise a signal processed by said first logic to produce a signal synchronised to said second clock domain; a synchronised signal output operable to export from said data processor said synchronised signal output from said synchroniser; and a signal input operable to import a signal to said data processor, said data processor being operable to route said imported signal to said further logic; wherein said plurality of data processors are arranged to operate in parallel with each other and said data processing apparatus further comprises: combining logic arranged to receive said exported synchronised signals from each of said plurality of data processors and to combine said exported synchronised signals to prod

Abstract: Bus logic, a data processing apparatus and a method is disclosed. The bus logic is operable to couple a plurality of master logic units with a plurality of slave logic units to enable data transfers to occur, each master logic unit being operable to perform an address transfer which, when received by a specified one of the plurality of slave logic units, causes an associated data transfer to be performed between that master logic unit and the specified one of the plurality of slave logic units, each of the plurality of slave logic units being required to complete a data transfer, once initiated, prior to performing any further data transfers, at least one of the plurality of slave logic units being operable to perform data transfers in an order which differs from that in which associated address transfers were received by that slave logic unit.

Abstract: A direct memory access controller for controlling data transfer between a data source and a data destination comprising: a read/write port operable to receive data from said data source via a source bus and to output said received data to said data destination via a destination bus; wherein said direct memory access controller is operable in response to a predetermined number of clock pulses, to control said read/write port to output said received data said predetermined number of clock pulses after having received it. Also a direct memory access controller for controlling data transfer between a data source and a data destination comprising: a single read/write port comprising a read channel operable to receive data from said data source via a read path on a bus and a write channel operable to output said received data to said data destination via a write path on said bus, said read and write channel being operable to perform data reads and writes independently of each other.