Patents by Inventor Christopher Wrigley
Christopher Wrigley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230120610Abstract: Point of sale devices are disclosed. A register point-of-sale system may include: a register base; a customer screen that is removeable received by the register base; a merchant screen adjustably mounted on the register base; and a card reader integrated into the customer screen. A mobile payment terminal system may include: a mobile payment terminal comprising a wireless card reader, magnetic stripe reader, slot that receives a chip card, a screen, and an integrated receipt printer; and a dock that removably receives the mobile payment terminal. A mobile card reader system may include a cylindrical mobile card reader comprising a screen, a wireless card reader, a magnetic stripe reader, a slot that receives a chip card, and a plurality of base slots that receive a plurality of base latches; and a cylindrical base with an angled end and latches.Type: ApplicationFiled: October 18, 2022Publication date: April 20, 2023Inventors: Patrick GUINDON, John FRERICHS, Inna LOBEL, Francois D NGUYEN, Jung Soo PARK, Kebei LI, Adam Christopher WRIGLEY
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Publication number: 20140131442Abstract: A card reader for use with a mobile device includes a card reader body having an information reading area configured to receive a card, an information reader configured to read information stored on the card and a connection device disposed on the card reader body and configured to be removably connected to the mobile device. The card reader also includes a first arm extending in the first direction away from the card reader body and spaced apart from the connection device and an opposing second arm extending in the first direction away from the card reader body and spaced apart from the connection device. The first arm and the second arm are configured to contact the mobile device and limit movement of the card reader body with respect to the mobile device when the card reader body is connected to the mobile device via the connection device.Type: ApplicationFiled: October 29, 2013Publication date: May 15, 2014Applicant: Banc of America Merchant Services, LLCInventors: Matthew Morrow, Keith Alan Newbrough, Cormac Eubanks, Adam Christopher Wrigley, Francois Duc Nguyen, Quinn Slater Huffstetler
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Publication number: 20070174513Abstract: A buffer is disclosed for storing data being transferred using a plurality of control channels, a data item of said data being transferred between a data source and a data destination using one of said plurality of control channels, said buffer comprising: a data input port operable to receive said data being transferred using said plurality of control channels; a data output port operable to output data to be transferred using said plurality of control channels; and a data store operable to store data received from said data input port prior to it being output by said data output port, said data store comprising a plurality of storage locations each operable to store a data item, said storage locations being arranged in groups, a storage location being allocated to a group in dependence on the control channel that a data item that it stores is received from, such that each group comprises storage locations storing data items received from a same one of said plurality of control channels.Type: ApplicationFiled: January 23, 2006Publication date: July 26, 2007Applicant: ARM LimitedInventors: Christopher Wrigley, David Gwilt
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Publication number: 20070162651Abstract: The application discloses a direct memory access controller operable to control data transfer between a plurality of data source and data destination pairs comprising: at least one port operable to receive data from at least one data source and to output data to at least one data destination; and a channel operable to transfer data between said at least some of said plurality of data source and data destination pairs, said channel comprising registers operable to store data transfer control data, said data transfer control data comprising a source address of said data to be transferred, a destination address of said data to be transferred and control data, said data source address and said data destination address specifying said data source and data destination; wherein prior to a data transfer between a data source and data destination pair said direct memory access controller is operable to request data transfer control data corresponding to said data source and data destination pair from a memory and to sType: ApplicationFiled: December 15, 2006Publication date: July 12, 2007Applicant: ARM LIMITEDInventors: David Gwilt, Christopher Wrigley
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Publication number: 20070150771Abstract: A data processing apparatus comprising a plurality of data processors, each data processor comprising: first logic operable in a first clock domain and further logic operable in a second clock domain, said first and second clock domains being asynchronous with each other; a synchroniser operable to synchronise a signal processed by said first logic to produce a signal synchronised to said second clock domain; a synchronised signal output operable to export from said data processor said synchronised signal output from said synchroniser; and a signal input operable to import a signal to said data processor, said data processor being operable to route said imported signal to said further logic; wherein said plurality of data processors are arranged to operate in parallel with each other and said data processing apparatus further comprises: combining logic arranged to receive said exported synchronised signals from each of said plurality of data processors and to combine said exported synchronised signals to prodType: ApplicationFiled: December 22, 2005Publication date: June 28, 2007Applicant: ARM LimitedInventors: Antony Penton, Vladimir Vasekin, Andrew Rose, Paul Hughes, Christopher Wrigley
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Publication number: 20060075169Abstract: Bus logic, a data processing apparatus and a method is disclosed. The bus logic is operable to couple a plurality of master logic units with a plurality of slave logic units to enable data transfers to occur, each master logic unit being operable to perform an address transfer which, when received by a specified one of the plurality of slave logic units, causes an associated data transfer to be performed between that master logic unit and the specified one of the plurality of slave logic units, each of the plurality of slave logic units being required to complete a data transfer, once initiated, prior to performing any further data transfers, at least one of the plurality of slave logic units being operable to perform data transfers in an order which differs from that in which associated address transfers were received by that slave logic unit.Type: ApplicationFiled: September 30, 2004Publication date: April 6, 2006Applicant: ARM LIMITEDInventors: Anthony Harris, Bruce Mathewson, Christopher Wrigley
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Publication number: 20050182863Abstract: A direct memory access controller for controlling data transfer between a data source and a data destination comprising: a read/write port operable to receive data from said data source via a source bus and to output said received data to said data destination via a destination bus; wherein said direct memory access controller is operable in response to a predetermined number of clock pulses, to control said read/write port to output said received data said predetermined number of clock pulses after having received it. Also a direct memory access controller for controlling data transfer between a data source and a data destination comprising: a single read/write port comprising a read channel operable to receive data from said data source via a read path on a bus and a write channel operable to output said received data to said data destination via a write path on said bus, said read and write channel being operable to perform data reads and writes independently of each other.Type: ApplicationFiled: February 18, 2004Publication date: August 18, 2005Applicant: ARM LIMITED,Inventors: Christopher Wrigley, Patrick McGlew, Andrew Burdass, Bruce Mathewson
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Patent number: D770973Type: GrantFiled: September 2, 2015Date of Patent: November 8, 2016Assignee: VERIZON PATENT AND LICENSING INC.Inventors: Andrew Nicholas Toth, Ephrem Chemaly, Adam Christopher Wrigley, Daniel Sanchez
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Patent number: D956712Type: GrantFiled: July 13, 2020Date of Patent: July 5, 2022Assignee: Frog Design Inc.Inventors: Francois Nguyen, Inna Lobel, Adam Christopher Wrigley, Kebei Li, Jung Soo Park
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Patent number: D1016075Type: GrantFiled: October 19, 2021Date of Patent: February 27, 2024Assignee: JPMORGAN CHASE BANK , N.A.Inventors: Patrick Guindon, John Frerichs, Inna Lobel, Francois D Nguyen, Jung Soo Park, Kebei Li, Adam Christopher Wrigley