Patents by Inventor CHRISTOS MARGIOLAS

CHRISTOS MARGIOLAS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10409603
    Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate a source memory address information, and is to indicate a destination architecturally-visible storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result in the destination architecturally-visible storage location. The result to indicate whether a logical memory address corresponding to the source memory address information is in a persistent memory. Other processors, methods, systems, and instructions are disclosed.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Sara S. Baghsorkhi, Christos Margiolas
  • Publication number: 20190138712
    Abstract: Example implementations are directed to systems and methods to load a native library including a core library in an isolated execution environment sandbox; periodically request an updated version of the core library from a registry; in response to requests from the application, authenticate the request via an interaction filter and validate information from the updated version of the core library for the request; and deliver the validated information to the application.
    Type: Application
    Filed: May 31, 2018
    Publication date: May 9, 2019
    Inventor: Christos Margiolas
  • Publication number: 20190138930
    Abstract: Example implementations are directed to systems and methods to process content employing a model for characterizing targeted content where the model is trained to flag indefinable user information; analyze the content to develop a sensitive data index based on content that is flagged by the model; and apply machine learning to generate characterization data and contextual data for the information associated with one or more users based on the sensitive data index, where the machine learning utilizes content adjacent to the information associated with one or more users and the sensitive data index in a neural network to output substitute terms.
    Type: Application
    Filed: May 31, 2018
    Publication date: May 9, 2019
    Inventor: Christos Margiolas
  • Publication number: 20190139098
    Abstract: Example implementations are directed to systems and methods to select content to publish that include receiving bids for content submissions for a publication opportunity; analyze each of the content submissions to determine a quality classification and contextual data; apply machine learning to generate a suitability score for each content submission; and select a content submission for the publication opportunity based on the on the bids, quality classification, and suitability score for the set of content submissions in view of a selection policy. According to an example implementation, content of the selected content submission is provided to publish.
    Type: Application
    Filed: May 31, 2018
    Publication date: May 9, 2019
    Inventor: Christos Margiolas
  • Publication number: 20190138511
    Abstract: Example implementations are directed to systems and methods to receive content associated with a user's digital activities in a source form; apply a conversion framework based on the source form that outputs the content as data in a development form; determine contextual terms of the data in the development form; gather environmental information associated with the content and user's digital activities; generate a primary indexer and secondary indexer to map a set of individual identifiers to the data; apply machine learning to generate characterization data and contextual data based on the environmental information, where the machine learning; utilizes the primary indexer and secondary indexer in a neural network to output a live model; update the live model with feedback; process the data with the live model and feedback to preform real-time analysis and data placement to package the analysis to a publisher.
    Type: Application
    Filed: May 15, 2018
    Publication date: May 9, 2019
    Inventor: Christos Margiolas
  • Patent number: 10025570
    Abstract: In one example, a system for modifying applications to support incremental checkpoints can include logic to generate a dominator tree based on a control flow graph for source code, wherein the control flow graph and the dominator tree comprise a plurality of nodes corresponding to basic blocks of the source code. The processor can select a region based on a leaf node of the dominator tree, the region based on an instruction threshold, and insert a first set of commit instructions into the source code based on entry points into the region and insert a second set of commit instructions into the source code based on exit points from the region. The processor can update the dominator tree to exclude the selected region and compile the source code into an executable application, wherein the first set of commit instructions and the second set of commit instructions enable incremental checkpoints.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Sara S. Baghsorkhi, Christos Margiolas
  • Publication number: 20180189062
    Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate a source memory address information, and is to indicate a destination architecturally-visible storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result in the destination architecturally-visible storage location. The result to indicate whether a logical memory address corresponding to the source memory address information is in a persistent memory. Other processors, methods, systems, and instructions are disclosed.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Applicant: Intel Corporation
    Inventors: Sara S. Baghsorkhi, Christos Margiolas
  • Publication number: 20180088916
    Abstract: In one example, a system for modifying applications to support incremental checkpoints can include logic to generate a dominator tree based on a control flow graph for source code, wherein the control flow graph and the dominator tree comprise a plurality of nodes corresponding to basic blocks of the source code. The processor can select a region based on a leaf node of the dominator tree, the region based on an instruction threshold, and insert a first set of commit instructions into the source code based on entry points into the region and insert a second set of commit instructions into the source code based on exit points from the region. The processor can update the dominator tree to exclude the selected region and compile the source code into an executable application, wherein the first set of commit instructions and the second set of commit instructions enable incremental checkpoints.
    Type: Application
    Filed: September 28, 2016
    Publication date: March 29, 2018
    Applicant: Intel Corporation
    Inventors: Sara S. Baghsorkhi, Christos Margiolas
  • Publication number: 20160147577
    Abstract: Systems and methods for adaptive thread control in a portable computing device (PCD) are provided. During operation a plurality of parallelized tasks for an application on the PCD are created. The application is executed with at least one processor of the PCD processing at least one main thread of the application. A determination is made whether a portion of the application being executed includes one or more of the parallelized tasks. A determination is made whether to perform the parallelized tasks in parallel. Based on the determination whether to perform the parallelized tasks in parallel, the parallelized tasks are executed with the at least one main thread of the application if the determination is not to perform the parallelized tasks in parallel, or if the determination is to perform the parallelized tasks in parallel, at least one worker thread is activated to execute the parallelized task in parallel with the main thread.
    Type: Application
    Filed: November 25, 2014
    Publication date: May 26, 2016
    Inventors: JAMES MICHAEL ARTMEIER, SUMIT SUR, ROBERT S. DREYER, MICHAEL D. SHARP, JAMES L. ESLIGER, WISLON KWAN, CHRISTOS MARGIOLAS
  • Publication number: 20160139901
    Abstract: Systems, methods, and computer programs are disclosed for performing runtime auto-parallelization of application code. One embodiment of such a method comprises receiving application code to be executed in a multi-processor system. The application code comprises an injected code cost computation expression for at least one loop in the application code defining a serial workload for processing the loop. A runtime profitability check of the loop is performed based on the injected code cost computation expression to determine whether the serial workload can be profitably parallelized. If the serial workload can be profitably parallelized, the loop is executed in parallel using two or more processors in the multi-processor system.
    Type: Application
    Filed: February 12, 2015
    Publication date: May 19, 2016
    Inventors: CHRISTOS MARGIOLAS, ROBERT SCOTT DREYER, JASON KIM, MICHAEL DOUGLAS SHARP