Abstract: The peeling stress between a Cu line and a capping layer thereon, after via patterning, is reduced by varying the shape of the via and positioning the via to increase the space between the via and the line edge, thereby increasing electromigration lifetime. Embodiments include varying the shape of the via, as by forming an oval or rectangular shape via, such that the ratio of the minor axis of the oval to the line with or the ratio of the width of the rectangle to the line width is less than about 0.7.

Abstract: A via is formed in contact with a conductive line, whereby the via is offset from the conductive line so that the via extends beyond the conductive line. In accordance with a specific embodiment, a portion of the via contacts a sidewall of the conductive line.

Abstract: The peeling stress between a Cu line and a capping layer thereon, after via patterning, is reduced by varying the shape of the via and positioning the via to increase the space between the via and the line edge, thereby increasing electromigration lifetime. Embodiments include varying the shape of the via, as by forming an oval or rectangular shape via, such that the ratio of the minor axis of the oval to the line with or the ratio of the width of the rectangle to the line width is less than about 0.7.

Abstract: A method for forming a semiconductor structure having a metal gate with a controlled work function includes the step of forming a precursor having a substrate with active regions separated by a channel, a temporary gate over the channel and within a dielectric layer. The temporary gate is removed to form a recess with a bottom and sidewalls in the dielectric layer. A non-silicon containing metal layer is deposited in the recess. Silicon is incorporated into the metal layer and a metal is deposited on the metal layer. The incorporation of the silicon is achieved by silane treatments that are performed before, after or both before and after the depositing of the metal layer. The amount of silicon incorporated into the metal layer controls the work function of the metal gate that is formed.

Abstract: Microminiaturized semiconductor devices are fabricated with a replacement metal gate and a high-k tantalum oxide or tantalum oxynitride gate dielectric with significantly reduced carbon. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing a thin tantalum film, as by PVD at a thickness of 25 ? to 60 ? lining the opening, and then conducting thermal oxidation, as at a temperature of 100° C. to 500° C., in flowing oxygen or ozone to form a high-k tantalum oxide gate dielectric layer, or in oxygen and N2O or ozone and N2O ammonia to form a high-k tantalum oxynitride gate dielectric. Alternatively, oxidation can be conducted in an oxygen or ozone plasma to form the high-k tantalum oxide layer, or in a plasma containing N2O and oxygen or ozone to form the high-k tantalum oxynitride gate dielectric layer.

Abstract: A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such that the nitrogen content increases from the bottom of the layer adjacent the gate dielectric layer upwardly. Other embodiments include forming the intrinsic electric field to control the work function by doping one or more metal layers and forming metal alloys. Embodiments further include the use of barrier layers when forming metal gate electrodes.

Abstract: According to one exemplary embodiment, a method for forming a contact over a silicide layer situated in a semiconductor die comprises a step of depositing a barrier layer on sidewalls of a contact hole and on a native oxide layer situated at a bottom of the contact hole, where the sidewalls are defined by the contact hole in a dielectric layer. The step of depositing the barrier layer on the sidewalls of the contact hole and on the native oxide layer can be optimized such that the barrier layer has a greater thickness at a top of the contact hole than a thickness at the bottom of the contact hole. According to this exemplary embodiment, the method further comprises a step of removing a portion of the barrier layer and the native oxide layer situated at the bottom of the contact hole to expose the silicide layer.

Abstract: The present invention is a dual-level flash memory cell design that stores 3 or more bits of information per transistor. The dual-level memory cell stores two lower bits in a first level and stores an upper bit in a second level. The lower bits are programmed, erased and read by alternate modes of operation wherein active regions operate as source and drain, and then drain and source. The upper bit is programmed and erased independent of the lower bits. However, reading of the upper bit depends upon read values of the lower bits. Additional levels are employed to store more than 3 bits of information.

Abstract: A composite ?-Ta/graded tantalum nitride/TaN barrier layer is formed in Cu interconnects with a structure designed for improved wafer-to-wafer uniformity, electromigration resistance and reliability, reduced contact resistance, and increased process margin. Embodiments include a dual damascene structure in a low-k interlayer dielectric comprising Cu and a composite barrier layer comprising an initial layer of TaN on the low-k material, a graded layer of tantalum nitride on the initial TaN layer and a continuous ?-Ta layer on the graded tantalum nitride layer. Embodiments include forming the initial TaN layer at a thickness sufficient to ensure deposition of ?-Ta, e.g., as at a thickness of bout 50 ? to about 100 ?. Embodiments include composite barrier layers having a thickness ratio of ?-Ta and graded tantalum nitride: initial TaN of about 2.5:1 to about 3.5:1 for improved electromigration resistance and wafer-to-wafer uniformity.

Abstract: A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, and a via extending through the first dielectric layer, the second etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The second etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the first dielectric layer is disposed over the second etch stop layer. The via can also have rounded corners. A third etch stop layer can also be disposed between the first diffusion barrier layer and the second etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer.

Abstract: According to one exemplary embodiment, a method for forming a contact over a silicide layer situated in a semiconductor die comprises a step of depositing a barrier layer on sidewalls of a contact hole and on a native oxide layer situated at a bottom of the contact hole, where the sidewalls are defined by the contact hole in a dielectric layer. The step of depositing the barrier layer on the sidewalls of the contact hole and on the native oxide layer can be optimized such that the barrier layer has a greater thickness at a top of the contact hole than a thickness at the bottom of the contact hole. According to this exemplary embodiment, the method further comprises a step of removing a portion of the barrier layer and the native oxide layer situated at the bottom of the contact hole to expose the silicide layer.

Abstract: A method for forming a semiconductor structure having a metal gate with a controlled work function includes the step of forming a precursor having a substrate with active regions separated by a channel, a temporary gate over the channel and within a dielectric layer. The temporary gate is removed to form a recess with a bottom and sidewalls in the dielectric layer. A non-silicon containing metal layer is deposited in the recess. Silicon is incorporated into the metal layer and a metal is deposited on the metal layer. The incorporation of the silicon is achieved by silane treatments that are performed before, after or both before and after the depositing of the metal layer. The amount of silicon incorporated into the metal layer controls the work function of the metal gate that is formed.

Abstract: A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such that the nitrogen content increases from the bottom of the layer adjacent the gate dielectric layer upwardly. Other embodiments include forming the intrinsic electric field to control the work function by doping one or more metal layers and forming metal alloys. Embodiments further include the use of barrier layers when forming metal gate electrodes.

Abstract: A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such that the nitrogen content increases from the bottom of the layer adjacent the gate dielectric layer upwardly. Other embodiments include forming the intrinsic electric field to control the work function by doping one or more metal layers and forming metal alloys. Embodiments further include the use of barrier layers when forming metal gate electrodes.

Abstract: A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The opening can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the opening, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from a material different than the first barrier layer, and the material of the first barrier layer can be selected from the group consisting of tantalum, titanium, tantalum nitride, titanium nitride, and tungsten nitride.

Abstract: A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, and a via extending through the first dielectric layer, the second etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The second etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the first dielectric layer is disposed over the second etch stop layer. The via can also have rounded corners. A third etch stop layer can also be disposed between the first diffusion barrier layer and the second etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer.

Abstract: In the present method of fabricating a semiconductor device, openings of different configurations (for example, different aspect ratios) are provided in a dielectric layer. Substantially undoped copper is deposited over the dielectric layer, filling the openings and extending above the dielectric layer, the different configurations of the openings providing an upper surface of the substantially undoped copper that is generally non-planar. A portion of the substantially undoped copper is removed to provide a substantially planar upper surface thereof, and a layer of doped copper is deposited on the upper surface of the substantially undoped copper. An anneal step is undertaken to difffuse the doping element into the copper in the openings.

Abstract: The reliability of Cu and Cu alloy interconnects is significantly enhanced by controlling the temperature of the electroplating solution during via opening filling to substantially prevent occlusion of the opening. Embodiments of the present invention include electroplating Cu or a Cu alloy from an electroplating solution at a temperature of about 20.degree. C. or less.