Abstract: A binary multiplier architecture which performs two's complement multiplication when the multiplier has 1's in more than half of its bits and performs unsigned binary multiplication by adding only shifted multiplicand vectors as a function of the multiplier all other times. Two's complement multiplication is performed by adding a multiplicand and a multiplier to two's complemented shifted multiplicand vectors as a function of the two's complement of the multiplier. To reduce the number of additions necessary, portions of the operands are merged with the shifted complemented vectors prior to addition of the shifted vectors. Carry lookahead may be provided to increase the speed.