Abstract: A system and method for fixed size texture compression utilizing dynamic alpha channel compression utilizes block-based compression. The method includes determining a first endpoint of a pixel block including four pixels, each pixel represented by a plurality of channels; determining a second endpoint of the pixel block, which is not the first endpoint; encoding the first endpoint and the second endpoint using a first plurality of bits; encoding a first quantization level using a second plurality of bits; encoding a second quantization level using a third plurality of bits; encoding an alpha map of the four pixels using a fourth plurality of bits; encoding a location of the first endpoint and a location of the second endpoint using a fifth plurality of bits; and storing an addressing indicator bit based on a distance between a value of the first endpoint and a value of the second endpoint.

Abstract: A system and method for fixed size texture compression utilizes a four pixel block. The method includes determining a first endpoint of a pixel block including four pixels, each pixel represented by a red channel, a green channel and a blue channel; determining a second endpoint of the pixel block, which is not the first endpoint; encoding the first endpoint and the second endpoint using a first plurality of bits; encoding a first quantization level using a second plurality of bits; encoding a second quantization level using a third plurality of bits; encoding a location of the first endpoint and a location of the second endpoint using a fourth plurality of bits; and encoding an addressing indicator bit based on a distance between a value of the first endpoint and a value of the second endpoint.

Abstract: Z-buffer compression may be useful for reducing memory usage bandwidth and for performance optimizations. A trackable method of doing the same may be additionally advantageous, as a lossy z-buffer compression scheme may noticeably alter a displayed object. A z-buffer compression unit receives an uncompressed tile, including a matrix of fragments, each representing a pixel and including a z-value. A minimum and maximum z-values of the tile are determined, and a comparison between each z-value of the tile to the minimum/maximum z-value generates a difference value. Basic tile information is then stored, and a compressed tile is stored in the z-buffer memory if the difference value is below a first threshold, such that each fragment is represented by a difference value and an indicator bit, to indicate if the difference is from the minimum z-value or the maximum z-value. The basic tile information includes the minimum z-value, and the maximum z-value.

Abstract: Z-buffer compression may be useful for reducing memory usage bandwidth and for performance optimizations. A trackable method of doing the same may be additionally advantageous, as a lossy z-buffer compression scheme may noticeably alter a displayed object. A z-buffer compression unit receives an uncompressed tile, including a matrix of fragments, each representing a pixel and including a z-value. A minimum and maximum z-values of the tile are determined, and a comparison between each z-value of the tile to the minimum/maximum z-value generates a difference value. Basic tile information is then stored, and a compressed tile is stored in the z-buffer memory if the difference value is below a first threshold, such that each fragment is represented by a difference value and an indicator bit, to indicate if the difference is from the minimum z-value or the maximum z-value. The basic tile information includes the minimum z-value, and the maximum z-value.

Abstract: An exemplary embodiment relates generally to methods and apparatus of operating a computing device to perform approximate memoizations. Computer code analysis methods, special hardware units, and run-time apparatus that allow limited errors to occur are disclosed. A computer code generation process, part of compiler or interpreter of a computing system, targeting to insert special instructions in the software code of a computer program is also disclosed, wherein the special instructions may embed information to manage the approximation of value memoizations. The presented technology may reduce the electric power consumption of a computing system by reusing the results or part of the results of previous arithmetic or memory operations. Run-time hardware apparatus to manage the elimination of the operations and control the error introduced by approximate value memoizations are also disclosed.

Abstract: A set of methods, techniques and hardware is described for compressing image data for memory bandwidth and memory storage reduction in graphics processing systems. The disclosed technology can be used for compressing image data sent to the frame buffer and/or image data residing in the frame buffer. The compression process can be based on an adaptive number of base color points and an adaptive number of quantized color points. An adaptive technique for compressing alpha values based on pre-calculated maps or using an estimated alpha value based on thresholds is also disclosed. An implementation of the disclosed methods has, for example, a low hardware overhead, low buffering requirements, and low and predefined compression latency. Also, the disclosed methods allow, for example, random accesses to compressed image data.

Abstract: A set of methods, techniques and hardware is described for compressing image data for memory bandwidth and memory storage reduction in graphics processing systems. The disclosed technology can be used for compressing image data sent to the frame buffer and/or image data residing in the frame buffer. The compression process can be based on an adaptive number of base color points and an adaptive number of quantized color points. An adaptive technique for compressing alpha values based on pre-calculated maps or using an estimated alpha value based on thresholds is also disclosed. An implementation of the disclosed methods has, for example, a low hardware overhead, low buffering requirements, and low and predefined compression latency. Also, the disclosed methods allow, for example, random accesses to compressed image data.

Abstract: An exemplary embodiment relates generally to methods and apparatus of operating a computing device to perform approximate memoizations. Computer code analysis methods, special hardware units, and run-time apparatus that allow limited errors to occur are disclosed. A computer code generation process, part of compiler or interpreter of a computing system, targeting to insert special instructions in the software code of a computer program is also disclosed, wherein the special instructions may embed information to manage the approximation of value memoizations. The presented technology may reduce the electric power consumption of a computing system by reusing the results or part of the results of previous arithmetic or memory operations. Run-time hardware apparatus to manage the elimination of the operations and control the error introduced by approximate value memoizations are also disclosed.

Abstract: The technology described in this application relates generally to computing processing systems and more specifically relates to systems that process data with resource intensive operations. Method and apparatus to lower the power consumption of the resource intensive operations are disclosed. Code analysis methods and run-time apparatus are presented that may eliminate the redundant operations (either complex calculations, memory fetches, or both). The techniques presented in this application are driven by special instructions inserted in the software code of the executing computer programs during the code generation process. Code analysis methods to insert the special instructions into the appropriate points in the source code of the target executing computer programs are presented. Run-time hardware mechanisms to support the potential elimination of redundant operations are also presented.

Abstract: The technology described in this application relates generally to computing processing systems and more specifically relates to systems that process data with resource intensive operations. Method and apparatus to lower the power consumption of the resource intensive operations are disclosed. Code analysis methods and run-time apparatus are presented that may eliminate the redundant operations (either complex calculations, memory fetches, or both). The techniques presented in this application are driven by special instructions inserted in the software code of the executing computer programs during the code generation process. Code analysis methods to insert the special instructions into the appropriate points in the source code of the target executing computer programs are presented. Run-time hardware mechanisms to support the potential elimination of redundant operations are also presented.