Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a package leadframe including a die pad, a first ridge formed at a first outer edge of the die pad, a second ridge formed at a second outer edge of the die pad opposite of the first outer edge and separate from the first ridge, and a plurality of leads surrounding the die pad. A semiconductor die is attached to the die pad by way of a die attach material. The semiconductor die is located on the die pad between the first ridge and the second ridge. An encapsulant encapsulates the semiconductor die and at least a portion of the package leadframe.

Abstract: A compound of Formula (I) below, or a pharmaceutically acceptable salt, stereoisomer, solvate, or prodrug thereof: in which R1, R2, R3, R5, R6, and R7 are defined as in the SUMMARY section. Further disclosed are a method of using the above-described compound, salt, stereoisomer, solvate, or prodrug for treating microbial infections and a pharmaceutical composition containing the same.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.

Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.

Abstract: A memory device includes first memory circuits and first memory controller. The first memory controller is configured to receive a first command from a first circuitry. When the first memory controller controls a first circuit in the first memory circuits to operate in an enable mode in response to the first command, the first memory controller is further configured to control remaining circuits in the first memory circuits to operate in a data retention mode in response to the first command.

Abstract: A memory comprising a memory array, including a plurality of blocks, and control circuits comprising logic to execute operations is provided. The operations include decoding a read setup burst command identifying (i) an address of a first read setup block in a set of read setup blocks and (ii) a number of read setup blocks, as candidates for read setup operations. The operations further including, in response to the decoding of the read setup burst command, performing a read setup burst operation on a plurality of read setup blocks of the set of read setup blocks.

Abstract: Disclosed are compositions comprising a) one or more polycarbonates; b) one or more first colorants; c) one or more flame retardants; and d) one or more particles having a melting point above the temperature at which polycarbonates are processed wherein the particles are coated with an organic polymer having a melting point above the processing temperature of the one or more polycarbonates; wherein the composition when molded exhibits a flecked appearance. The particles have a second colorant bound to the surface of the particles by the organic polymer. The organic polymer may be crosslinked. The one or more polycarbonates may comprise post-consumer recycled polycarbonates. Disclosed are molded products prepared from the disclosed compositions. The molded products exhibit good properties as disclosed herein. The molded products have a flecked appearance.

Abstract: A storage device includes a memory array and a memory controller. The memory controller generates read and write commands for the memory array. An error correction code engine for the storage device is operable to use a plurality of different codeword sizes, different code rates, or different ECC algorithms. Logic is included that applies a selected codeword size, code rate or ECC algorithm in dependence on the operating conditions of the memory array.

Abstract: A method for sensing temperature in memory die, memory die and memory with temperature sensing function are provides. The memory die includes at least one temperature monitoring for outputting a temperature status in the memory die; a temperature sensor, arranged in the memory die for sensing an operation temperature in the memory die; and a control logic unit, coupled to the temperature sensor for receiving the operation temperature and coupled to the temperature monitoring pin. The control logic unit compares the operation temperature and a threshold value received from outside of the memory die to generate a comparison result, and outputs the temperature status through the temperature monitoring according to the comparison result.

Abstract: A storage device includes a memory array and a memory controller. The memory controller generates read and write commands for the memory array. An error correction code engine for the storage device is operable to use a plurality of different codeword sizes, different code rates, or different ECC algorithms. Logic is included that applies a selected codeword size, code rate or ECC algorithm in dependence on the operating conditions of the memory array.

Abstract: A neurovascular age prediction system based on white matter and a method thereof are disclosed. An analysis device generates an individual space periventricular area mask and an individual space deep white matter mask by nonlinear space counterpoint technology and MNI152 brain template, and reversely transforms individual coordinates into a transition matrix, performs white matter hyperintensity (WMH) signal image processing on the T1 weighted image and the T2 fluid attenuated inversion recovery (FLAIR) image to generate a T1 weighted WMH signal image and a T2 FLAIR WMH signal image, then converts the Ti WMH signal image and the T2 FLAIR WMH signal image into logarithms of a periventricular white matter volume and a deep WMH volume based on the individual space periventricular area mask and the individual space deep white matter mask, and substitutes the logarithms into a neurovascular age prediction model to obtain a neurovascular age prediction result.

Abstract: An intelligent storage device and an intelligent storage method are provided. The intelligent storage device includes a storage space, an infrared sensor, a weight sensor, a transceiver, and a processor. The storage space is suitable for storing an object. The infrared sensor senses the storage space to generate infrared sensing data. The weight sensor senses the object in the storage space to generate weight sensing data. The processor is coupled to the infrared sensor, the weight sensor, and the transceiver, determines whether the object is placed in or removed from the storage space according to the infrared sensing data and the weight sensing data to generate an event record, and transmits the event record via the transceiver.

Abstract: A compound of Formula (I) below, or a pharmaceutically acceptable salt, stereoisomer, solvate, or prodrug thereof: (I), in which Ra, Rb, Rc, Rd, X1, X2, R1-R4, W, Z, and L are defined as in the SUMMARY section. Further disclosed are a method of using the above-described compound, salt, stereoisomer, solvate, or prodrug for treating HBV infection and a pharmaceutical composition containing same.

Abstract: A memory comprising a memory array, including a plurality of blocks, and control circuits comprising logic to execute operations is provided. The operations include decoding a read setup burst command identifying (i) an address of a first read setup block in a set of read setup blocks and (ii) a number of read setup blocks, as candidates for read setup operations. The operations further including, in response to the decoding of the read setup burst command, performing a read setup burst operation on a plurality of read setup blocks of the set of read setup blocks.

Abstract: A method for sensing temperature in memory die, memory die and memory with temperature sensing function are provides. The memory die includes at least one temperature monitoring for outputting a temperature status in the memory die; a temperature sensor, arranged in the memory die for sensing an operation temperature in the memory die; and a control logic unit, coupled to the temperature sensor for receiving the operation temperature and coupled to the temperature monitoring pin. The control logic unit compares the operation temperature and a threshold value received from outside of the memory die to generate a comparison result, and outputs the temperature status through the temperature monitoring according to the comparison result.

Abstract: A memory device includes first memory circuits and first memory controller. The first memory controller is configured to receive a first command from a first circuitry.

Abstract: A method of operating a memory is provided. The method includes, in response to an access of a block of memory updating a first queue to identify the accessed block in response to a determination that the block is not already identified in the first queue and a determination that the block is not already identified in a second queue, and updating the second queue to identify the accessed block of memory in response to a determination that the block is already identified in the first queue. The method further includes scanning the second queue to identify, as a read setup candidate, each block of the memory that is identified as present in the second queue longer than a threshold, and performing a read setup operation on a block of memory that has been identified as the read setup candidate.

Abstract: An intelligent storage device and an intelligent storage method are provided. The intelligent storage device includes a storage space, an infrared sensor, a weight sensor, a transceiver, and a processor. The storage space is suitable for storing an object. The infrared sensor senses the storage space to generate infrared sensing data. The weight sensor senses the object in the storage space to generate weight sensing data. The processor is coupled to the infrared sensor, the weight sensor, and the transceiver, determines whether the object is placed in or removed from the storage space according to the infrared sensing data and the weight sensing data to generate an event record, and transmits the event record via the transceiver.

Abstract: Disclosed are vinylidene substituted aromatic polymers which include a zinc salt. Disclosed is a method of reducing the total volatile organic components in a vinylidene substituted aromatic polymer. Disclosed is a method of making vinylidene substituted aromatic polymers which include a zinc salt. Disclosed is a masterbatch which includes a styrenic polymer, a zinc salt and optionally a pigment and methods of making the masterbatch. The masterbatch may be used in a method making a styrenic polymer molded part.