Patents by Inventor Chu-An Chung

Chu-An Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080246165
    Abstract: A semiconductor device (601) is provided which comprises a substrate (603); a semiconductor device (605) disposed on said substrate and having a first major surface; a first metal strap (615) which is in electrical contact with said substrate and which is adapted to provide power to a first region (608) of said semiconductor device; and a second metal strap (616) which is in electrical contact with said substrate and which is adapted to provide ground to a second region (609) of said semiconductor device.
    Type: Application
    Filed: April 4, 2007
    Publication date: October 9, 2008
    Inventors: Kevin J. Hess, Chu-Chung Lee, James W. Miller
  • Publication number: 20080242701
    Abstract: This invention relates to treating cancer or an angiogenesis-related disease using a compound of formula 1: wherein R1, R2, R3, R4, and n are defined herein.
    Type: Application
    Filed: June 3, 2008
    Publication date: October 2, 2008
    Applicant: National Health Research Institutes
    Inventors: Chiung-Tong Chen, Shu-Jen Chen, Ming-Chu Hsu, Der-Ren Hwang, Wen-Tai Li, Chu-Chung Lin
  • Publication number: 20080203588
    Abstract: A packaged integrated circuit has an integrated circuit over a support structure. A plurality of bond wires connected between active terminals of the integrated circuit and the support structure. An encapsulant overlies the support structure, the integrated circuit, and the bond wires. The encapsulant has a first open location in the encapsulant so that a first bond wire is exposed and a second open location in the encapsulant so that a second bond wire is exposed. First and second conductive structures are exposed outside the packaged integrated circuit and are located at the first and second open locations, respectively, and electrically connected to the first and second bond wires, respectively.
    Type: Application
    Filed: February 28, 2007
    Publication date: August 28, 2008
    Inventors: Kevin J. Hess, Chu-Chung Lee
  • Publication number: 20080198166
    Abstract: A vertex shader. The vertex shader comprises an instruction register file, a flow controller, a thread arbitrator, and an arithmetic logic unit (ALU) pipe. The instruction register file stores a plurality of instructions. The flow controller concurrently executing a plurality of threads, reads the instructions in order from the instruction register file for the threads and accesses vertex data for the threads. The thread arbitrator checks the dependency of instructions in the threads and selects the thread to execute in accordance with the result of the dependency check and a thread execution priority. The arithmetic logic unit (ALU) pipe receives the vertex data for executing the instructions of the thread selected by the thread arbitrator for three-dimensional (3D) graphics computations.
    Type: Application
    Filed: February 16, 2007
    Publication date: August 21, 2008
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Hsine-Chu Chung, Chit-Keng Huang, Ko-Fang Wang
  • Publication number: 20080179745
    Abstract: In some embodiments a method of forming a gold-aluminum electrical interconnect is described. The method may include interposing a diffusion retardant layer between the gold and the aluminum (1002), the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material; bringing into contact the diffusion retardant layer, the gold, and the aluminum (1004); forming alloys of gold and the diffusion retardant material in regions containing the material (1006) and forming gold-aluminum intermetallic compounds in regions substantially devoid of the material (1008); and forming a continuous electrically conducting path between the aluminum and the gold (1010). In some embodiments, a structure useful in a gold-aluminum interconnect is provided.
    Type: Application
    Filed: January 31, 2007
    Publication date: July 31, 2008
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Kevin J. Hess, Chu-Chung Lee
  • Publication number: 20080164593
    Abstract: A method of packaging a semiconductor includes providing a support structure. An adhesive layer is formed overlying the support structure and is in contact with the support structure. A plurality of semiconductor die is placed on the adhesive layer. The semiconductor die are laterally separated from each other and have electrical contacts that are in contact with the adhesive layer. A layer of encapsulating material is formed overlying and between the plurality of semiconductor die and has a distribution of filler material. A concentration of the filler material is increased in all areas laterally adjacent each of the plurality of semiconductor die.
    Type: Application
    Filed: January 5, 2007
    Publication date: July 10, 2008
    Inventors: Kevin J. Hess, Chu-Chung Lee, Robert J. Wenzel
  • Patent number: 7396838
    Abstract: A method of treating cancer including administering to a subject in need thereof an effective amount of a compound of the formula 1: wherein R1, R2, R3, R4, and n are as defined herein.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: July 8, 2008
    Assignee: National Health Research Institutes
    Inventors: Chiung-Tong Chen, Shu-Jen Chen, Ming-Chu Hsu, Der-Ren Hwang, Wen-Tai Li, Chu-Chung Lin
  • Publication number: 20080136016
    Abstract: A semiconductor package (10) uses a plurality of thermal conductors (56-64) that extend upward within an encapsulant (16) from one or more thermal bond pads (22, 24, 26) on a die (14) to disperse heat. The thermal conductors may be bond wires or conductive stud bumps and do not extend beyond a lateral edge of the die. One or more of the thermal conductors may be looped within the encapsulant and exposed at an upper surface of the encapsulant. In one form a heat spreader (68) is placed overlying the encapsulant for further heat removal. In another form the heat spreader functions as a power or ground terminal directly to points interior to the die via the thermal conductors. Active bond pads may be placed exclusively along the die's periphery or also included within the interior of the die.
    Type: Application
    Filed: February 19, 2008
    Publication date: June 12, 2008
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Kevin J. Hess, Chu-Chung Lee
  • Publication number: 20080122843
    Abstract: A logic unit is provided for performing operations in multiple threads on vertex data. The logic unit comprises a macro instruction register file, a flow control instruction register file, and a flow controller. The macro instruction register file stores macro blocks with each macro block including at least one instruction. The flow control instruction register file stores flow control instructions with each flow control instruction including at least one called macro block and dependency information of the called macro block.
    Type: Application
    Filed: July 20, 2006
    Publication date: May 29, 2008
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Hsine-Chu Chung, Ko-Fang Wang, Chit-Keng Huang
  • Patent number: 7378524
    Abstract: This invention relates to treating inflammatory and immune diseases with certain aminoquinoline compounds that bind to CXCR3 receptors. The aminoquinoline compounds are covered by the formula (I) shown below. Each variable is defined in the specification.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: May 27, 2008
    Assignee: Taigen Biotechnology Co., Ltd.
    Inventors: Chu-Chung Lin, Jen-Fuh Liu, Chih-Wei Chang, Shu-Jen Chen, Yibin Xiang, Pei-Chin Cheng, Jiing-Jyh Jan
  • Patent number: 7374971
    Abstract: An integrated circuit has a semiconductor substrate and an interconnect layer that mechanically relatively weak and susceptible to cracks and delamination. In the formation of the integrated circuit from a semiconductor wafer, a cut is made through the interconnect layer to form an edge of the interconnect layer. This cut may continue completely through the wafer thickness or stop short of doing so. In either case, after cutting through the interconnect layer, a reconditioning layer is formed on the edge of the interconnect layer. This reconditioning layer seals the existing cracks and delaminations and inhibits the further delamination or cracking of the interconnect layer. The sealing layer may be formed, for example, before the cut through the wafer, after the cut through the wafer but before any packaging, or after performing wirebonding between the interconnect layer and an integrated circuit package.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: May 20, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yuan Yuan, Kevin J. Hess, Chu-Chung Lee, Tu-Anh Tran, Donna Woosley, legal representative, Alan H. Woosley
  • Publication number: 20080108632
    Abstract: This invention relates to the compounds of formula (I) shown below. Each variable in formula (I) is defined in the specification. These compounds can be used to treat hepatitis C virus infection.
    Type: Application
    Filed: November 2, 2007
    Publication date: May 8, 2008
    Applicant: TaiGen Biotechnology Co., Ltd.
    Inventors: Chu-chung Lin, Pei-chin Cheng, Yo-chin Liu, Chen-fu Liu, Chi-Hsin Richard King
  • Patent number: 7355289
    Abstract: A semiconductor package (10) uses a plurality of thermal conductors (56-64) that extend upward within an encapsulant (16) from one or more thermal bond pads (22, 24, 26) on a die (14) to disperse heat. The thermal conductors may be bond wires or conductive stud bumps and do not extend beyond a lateral edge of the die. One or more of the thermal conductors may be looped within the encapsulant and exposed at an upper surface of the encapsulant. In one form a heat spreader (68) is placed overlying the encapsulant for further heat removal. In another form the heat spreader functions as a power or ground terminal directly to points interior to the die via the thermal conductors. Active bond pads may be placed exclusively along the die's periphery or also included within the interior of the die.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: April 8, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kevin J. Hess, Chu-Chung Lee
  • Publication number: 20080038912
    Abstract: A method is provided for forming peripheral contacts between a die and a substrate. In accordance with the method, a die (305) is provided which has first and second opposing major surfaces, wherein the first major surface is attached to a substrate (303) having a first group (323) of contact pads disposed thereon, and wherein the second major surface has a second group (311) of contact pads disposed thereon. An electrically conductive pathway (326) is formed between the first and second groups of contacts with an electrically conductive polymeric composition.
    Type: Application
    Filed: August 11, 2006
    Publication date: February 14, 2008
    Inventors: Kevin J. Hess, Chu-Chung Lee, James W. Miller
  • Publication number: 20070194460
    Abstract: A bond pad for an electronic device such as an integrated circuit makes electrical connection to an underlying device via an interconnect layer. The bond pad has a first layer of a material that is aluminum and copper and a second layer, over the first layer, of a second material that is aluminum and is essentially free of copper. The second layer functions as a cap to the first layer for preventing copper in the first layer from being corroded by residual chemical elements. A wire such as a gold wire may be bonded to the second layer of the bond pad.
    Type: Application
    Filed: February 23, 2006
    Publication date: August 23, 2007
    Inventors: Chu-Chung Lee, Kevin Hess
  • Patent number: 7256488
    Abstract: A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: August 14, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yaping Zhou, Chu-Chung Lee
  • Publication number: 20070087067
    Abstract: A die (10) for an integrated circuit comprising an active area (22) is provided. The die (10) may further comprise a first ring (12) in a peripheral region of the die (10) at least partially surrounding the active area (22), wherein the first ring (12) may comprise a plurality of polygon shaped cells (32, 36). The die (10) may further comprise a second ring (14) surrounding the first ring (12), wherein the second ring (14) may comprise a plurality of polygon shaped cells (32, 36).
    Type: Application
    Filed: October 18, 2005
    Publication date: April 19, 2007
    Inventors: Yuan Yuan, Chu-Chung Lee, Tu-Anh Tran, Paul Winebarger
  • Patent number: 7183413
    Abstract: This invention relates to treating inflammatory and immune diseases with certain aminoquinoline compounds that bind to CXCR3 receptors. The aminoquinoline compounds are covered by the formula (I) shown below. Each variable is defined in the specification.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: February 27, 2007
    Assignee: Taigen Biotechnology
    Inventors: Chu-Chung Lin, Jen-Fuh Liu, Chih-Wei Chang, Shu-Jen Chen, Yibin Xiang, Pei-Chin Cheng, Jiing-Jyh Jan
  • Publication number: 20070023880
    Abstract: A semiconductor package (10) uses a plurality of thermal conductors (56-64) that extend upward within an encapsulant (16) from one or more thermal bond pads (22, 24, 26) on a die (14) to disperse heat. The thermal conductors may be bond wires or conductive stud bumps and do not extend beyond a lateral edge of the die. One or more of the thermal conductors may be looped within the encapsulant and exposed at an upper surface of the encapsulant. In one form a heat spreader (68) is placed overlying the encapsulant for further heat removal. In another form the heat spreader functions as a power or ground terminal directly to points interior to the die via the thermal conductors. Active bond pads may be placed exclusively along the die's periphery or also included within the interior of the die.
    Type: Application
    Filed: July 29, 2005
    Publication date: February 1, 2007
    Inventors: Kevin Hess, Chu-Chung Lee
  • Publication number: 20060264462
    Abstract: The invention relates to novel imidazolamino compounds. Also disclosed are methods of treating cancer by using one of these compounds and pharmaceutical compositions containing one of these compounds.
    Type: Application
    Filed: July 28, 2006
    Publication date: November 23, 2006
    Inventors: Chiung-Tong Chen, Wen-Tai Li, Der-Ren Hwang, Chu-Chung Lin