Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

Abstract: Embodiments are generally directed to an apparatus utilizing computer on package construction. An embodiment of a computer includes a substrate; one or more semiconductor devices, the one or more semiconductor devices being direct chip attached to the substrate, the one or more semiconductor devices including a central processing unit (CPU); and one or more additional components installed on the substrate, wherein the computer excludes I/O components.

Abstract: Embodiments are generally directed to an apparatus utilizing computer on package construction. An embodiment of a computer includes a substrate; one or more semiconductor devices, the one or more semiconductor devices being direct chip attached to the substrate, the one or more semiconductor devices including a central processing unit (CPU); and one or more additional components installed on the substrate, wherein the computer excludes I/O components.

Abstract: An apparatus including a circuit substrate having a plurality of contactor pins extending between two opposing surfaces; and at least one capacitor mounted on one of the two opposing surfaces of the circuit substrate.

Abstract: An apparatus including a circuit substrate having a plurality of contactor pins extending between two opposing surfaces; and at least one capacitor mounted on one of the two opposing surfaces of the circuit substrate.

Abstract: An apparatus for testing electronic devices such as integrated circuits. In one embodiment, an apparatus for testing electronic devices is disclosed that includes a housing such as a test contactor housing which has a plurality of test contactor pins that extend therethrough. The plurality of test contactor pins include a first set of power pins, a second set of ground pins, and a third set of signal pins. A printed circuit board, attached to the housing, has a first ground plane and a first power plane. The power pins are electrically coupled to the first power plane and the ground pins are electrically coupled to the first ground plane. The first set of power pins, the second set of ground pins, and the third set of signal pins extend through the printed circuit board.

Abstract: An apparatus for testing electronic devices such as integrated circuits. In one embodiment, an apparatus for testing electronic devices is disclosed that includes a housing such as a test contactor housing which has a plurality of test contactor pins that extend therethrough. The plurality of test contactor pins include a first set of power pins, a second set of ground pins, and a third set of signal pins. A printed circuit board, attached to the housing, has a first ground plane and a first power plane. The power pins are electrically coupled to the first power plane and the ground pins are electrically coupled to the first ground plane. The first set of power pins, the second set of ground pins, and the third set of signal pins extend through the printed circuit board.