Patents by Inventor Chu Aun Lim

Chu Aun Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190287872
    Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.
    Type: Application
    Filed: March 19, 2018
    Publication date: September 19, 2019
    Applicant: INTEL CORPORATION
    Inventors: Eng Huat Goh, Jiun Hann Sir, Min Suet Lim, Richard C. Stamey, Chu Aun Lim, Jimin Yao
  • Patent number: 10317938
    Abstract: Embodiments are generally directed to an apparatus utilizing computer on package construction. An embodiment of a computer includes a substrate; one or more semiconductor devices, the one or more semiconductor devices being direct chip attached to the substrate, the one or more semiconductor devices including a central processing unit (CPU); and one or more additional components installed on the substrate, wherein the computer excludes I/O components.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: June 11, 2019
    Assignee: INTEL CORPORATION
    Inventors: Eng Huat Goh, Khai Ern See, Damien Weng Kong Chong, Min Suet Lim, Ping Ping Ooi, Chu Aun Lim, Jimmy Huat Since Huang, Poh Tat Oh, Teong Keat Beh, Jackson Chung Peng Kong, Fern Nee Tan, Jenn Chuan Cheng
  • Publication number: 20160216731
    Abstract: Embodiments are generally directed to an apparatus utilizing computer on package construction. An embodiment of a computer includes a substrate; one or more semiconductor devices, the one or more semiconductor devices being direct chip attached to the substrate, the one or more semiconductor devices including a central processing unit (CPU); and one or more additional components installed on the substrate, wherein the computer excludes I/O components.
    Type: Application
    Filed: January 23, 2015
    Publication date: July 28, 2016
    Inventors: Eng Huat Goh, Khai Ern See, Damien Weng Kong Chong, Min Suet Lim, Ping Ping Ooi, Chu Aun Lim, Jimmy Huat Since Huang, Poh Tat Oh, Teong Keat Beh, Jackson Chung Peng Kong, Fern Nee Tan, Jenn Chuan Cheng
  • Patent number: 6885207
    Abstract: An apparatus including a circuit substrate having a plurality of contactor pins extending between two opposing surfaces; and at least one capacitor mounted on one of the two opposing surfaces of the circuit substrate.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: April 26, 2005
    Assignee: Intel Corporation
    Inventors: Kok Hong Chan, Chu Aun Lim, Tark Wooi Fong
  • Publication number: 20030206033
    Abstract: An apparatus including a circuit substrate having a plurality of contactor pins extending between two opposing surfaces; and at least one capacitor mounted on one of the two opposing surfaces of the circuit substrate.
    Type: Application
    Filed: May 16, 2003
    Publication date: November 6, 2003
    Inventors: Kok Hong Chan, Chu Aun Lim, Tark Wooi Fong
  • Patent number: 6597190
    Abstract: An apparatus for testing electronic devices such as integrated circuits. In one embodiment, an apparatus for testing electronic devices is disclosed that includes a housing such as a test contactor housing which has a plurality of test contactor pins that extend therethrough. The plurality of test contactor pins include a first set of power pins, a second set of ground pins, and a third set of signal pins. A printed circuit board, attached to the housing, has a first ground plane and a first power plane. The power pins are electrically coupled to the first power plane and the ground pins are electrically coupled to the first ground plane. The first set of power pins, the second set of ground pins, and the third set of signal pins extend through the printed circuit board.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: July 22, 2003
    Assignee: Intel Corporation
    Inventors: Kok Hong Chan, Chu Aun Lim, Tark Wooi Fong
  • Publication number: 20020105349
    Abstract: An apparatus for testing electronic devices such as integrated circuits. In one embodiment, an apparatus for testing electronic devices is disclosed that includes a housing such as a test contactor housing which has a plurality of test contactor pins that extend therethrough. The plurality of test contactor pins include a first set of power pins, a second set of ground pins, and a third set of signal pins. A printed circuit board, attached to the housing, has a first ground plane and a first power plane. The power pins are electrically coupled to the first power plane and the ground pins are electrically coupled to the first ground plane. The first set of power pins, the second set of ground pins, and the third set of signal pins extend through the printed circuit board.
    Type: Application
    Filed: February 11, 2002
    Publication date: August 8, 2002
    Inventors: Kok Hong Chan, Chu Aun Lim, Tark Wooi Fong