Abstract: Races and hazards in simulated logic designs are more easily detected if the logic simualtor is able to warn the designer of the presence of glitches. A glitch wall occur at the output of a logic device if an input condition causes the output to begin to change but the input condition is not present for sufficient time to allow the output to reach its stable state. The logic evaluator is the component of the logic simulator which is responsible for determining the output of a simulated device when the inputs to that device are known. The glitch detecting logic evaluator according to the present invention provides glitch detection by forcing the simulated device output to the undefined state when the device inputs change in a manner which does not allow the change to propagate to the output before a subsequent change occurs. The algorithms are designed for implementation in hardware for high performance logic simulation.

Abstract: Logic simulation is performed using special purpose hardware which operates in either one of two simulation modes. The machine allows detailed timing simulation where each device may be programmed with a delay time of zero, one, or multiple simulation time units. In addition, the machine supports zero and unit delay simulation in a high performance "unit delay" mode. The logic simulation function is partitioned into six sub-functions which are implemented in a single stage of a six-stage pipeline. The pipeline stages which implement the multi-unit delay time queue management may be switched to perform a different algorithm for unit delay simulation. The machine is able to perform extremely fast functional circuit testing and to perform detailed timing simulation without changing the circuit "netlist".