Patents by Inventor Chu-Chen Fu
Chu-Chen Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220199686Abstract: A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures.Type: ApplicationFiled: March 14, 2022Publication date: June 23, 2022Inventors: Lei WAN, Jordan KATINE, Tsai-Wei WU, Chu-Chen FU
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Patent number: 10050194Abstract: First electrically conductive lines can be formed over a substrate. A two-dimensional array of vertical stacks can be formed, each of which includes a first electrode, an in-process resistive memory material portion, and a second electrode over the first electrically conductive line. The sidewalls of the in-process resistive memory material portions are laterally recessed with respect to sidewalls of the first electrode and the second electrode to form resistive memory material portions having reduced lateral dimensions. A dielectric material layer is formed by an anisotropic deposition to form annular cavities that laterally surround a respective one of the resistive memory material portions. Second electrically conductive lines can be formed on the second electrodes.Type: GrantFiled: April 4, 2017Date of Patent: August 14, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Federico Nardi, Chu-Chen Fu
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Patent number: 10026782Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.Type: GrantFiled: June 26, 2017Date of Patent: July 17, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Yoichiro Tanaka, Yangyin Chen, Chu-Chen Fu, Christopher Petti
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Publication number: 20170309681Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.Type: ApplicationFiled: June 26, 2017Publication date: October 26, 2017Applicant: SANDISK TECHNOLOGIES LLCInventors: Yoichiro Tanaka, Yangyin Chen, Chu-Chen Fu, Christopher Petti
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Publication number: 20170236871Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.Type: ApplicationFiled: March 30, 2016Publication date: August 17, 2017Applicant: SANDISK TECHNOLOGIES INC.Inventors: Yoichiro Tanaka, Yangyin Chen, Chu-Chen Fu, Christopher Petti
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Patent number: 9735202Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.Type: GrantFiled: March 30, 2016Date of Patent: August 15, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Yoichiro Tanaka, Yangyin Chen, Chu-Chen Fu, Christopher Petti
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Patent number: 9054308Abstract: A fabrication process for a resistance-switching memory cell uses metal oxide as a resistance-switching material. A metal oxide film having an initial stoichiometry is deposited on an electrode using atomic layer deposition. A changed stoichiometry is provided for a portion of the metal oxide film using a plasma reduction process, separate from the atomic layer deposition, and another electrode is formed adjacent to the changed stoichiometry portion. The film deposition and the plasma reduction can be performed in separate chambers where conditions such as temperature are optimized. The metal oxide film may be deposited on a vertical sidewall in a vertical bit line 3d memory device. Optionally, the mean free path of hydrogen ions during the plasma reduction process is adjusted to increase the uniformity of the vertical metal oxide film. The adjustment can involve factors such as RF power, pressure and a bias of the wafer.Type: GrantFiled: March 4, 2014Date of Patent: June 9, 2015Assignee: SanDisk 3D LLCInventors: Tong Zhang, Timothy James Minvielle, Chu-Chen Fu, Wipul Jayasekara
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Patent number: 9034689Abstract: Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air break. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element.Type: GrantFiled: March 21, 2013Date of Patent: May 19, 2015Assignee: SanDisk 3D LLCInventors: Deepak C. Sekar, Franz Kreupl, Peter Rabkin, Chu-Chen Fu
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Publication number: 20140252298Abstract: In some aspects, a memory cell is provided that includes a first conducting layer, a reversible resistance switching element above the first conducting layer, a second conducting layer above the reversible resistance switching element, and a liner disposed about a sidewall of the reversible resistance switching element. The reversible resistance switching element includes a first metal oxide material, and the liner includes the first metal oxide material. Numerous other aspects are provided.Type: ApplicationFiled: March 10, 2013Publication date: September 11, 2014Applicant: SANDISK 3D LLCInventors: Yubao Li, Chu-Chen Fu, Timothy James Minvielle, Huiwen Xu
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Patent number: 8551850Abstract: A method of forming a reversible resistance-switching metal-insulator-metal structure is provided, the method including forming a first non-metallic conducting layer, forming a non-conducting layer above the first non-metallic conducting layer, forming a second non-metallic conducting layer above the non-conducting layer, etching the first non-metallic conducting layer, non-conducting layer and second non-metallic conducting layer to form a pillar, and disposing a carbon material layer about a sidewall of the pillar. Other aspects are also provided.Type: GrantFiled: December 7, 2009Date of Patent: October 8, 2013Assignee: SanDisk 3D LLCInventors: Yubao Li, Chu-Chen Fu, Jingyan Zhang
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Publication number: 20130234099Abstract: Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air break. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element.Type: ApplicationFiled: March 21, 2013Publication date: September 12, 2013Applicant: SANDISK 3D LLCInventors: Deepak C. Sekar, Franz Kreupl, Raghuveer S. Makala, Peter Rabkin, Chu-Chen Fu, Tong Zhang
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Patent number: 8520424Abstract: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.Type: GrantFiled: June 9, 2011Date of Patent: August 27, 2013Assignee: SanDisk 3D LLCInventors: Franz Kreupl, Abhijit Bandyopadhyay, Yung-Tin Chen, Chu-Chen Fu, Wipul Pemsiri Jayasekara, James Kai, Raghuveer S. Makala, Peter Rabkin, George Samachisa, Jingyan Zhang
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Publication number: 20130075685Abstract: In some aspects, a reversible resistance-switching metal-insulator-metal stack is provided that includes a first conducting layer, a carbon nano-tube (“CNT”) material above the first conducting layer, a second conducting layer above the CNT material, and an air gap between the first conducting layer and the CNT material. Numerous other aspects are provided.Type: ApplicationFiled: September 22, 2011Publication date: March 28, 2013Inventors: Yubao Li, Chu-Chen Fu
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Patent number: 8395927Abstract: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has a resistance-switching layer, a conductive intermediate layer, and first and second electrodes at either end of the RSME. A breakdown layer is electrically between, and in series with, the second electrode and the intermediate layer. The breakdown layer maintains a resistance of at least about 1-10 M? while in a conductive state. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.Type: GrantFiled: June 9, 2011Date of Patent: March 12, 2013Assignee: SanDisk 3D LLCInventors: Franz Kreupl, Chu-Chen Fu, Yibo Nian
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Publication number: 20110310656Abstract: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has a resistance-switching layer, a conductive intermediate layer, and first and second electrodes at either end of the RSME. A breakdown layer is electrically between, and in series with, the second electrode and the intermediate layer. The breakdown layer maintains a resistance of at least about 1-10 M? while in a conductive state. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.Type: ApplicationFiled: June 9, 2011Publication date: December 22, 2011Inventors: Franz Kreupl, Chu-Chen Fu, Yibo Nian
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Publication number: 20110310655Abstract: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.Type: ApplicationFiled: June 9, 2011Publication date: December 22, 2011Inventors: Franz Kreupl, Abhijit Bandyopadhyay, Yung-Tin Chen, Chu-Chen Fu, Wipul Pemsiri Jayasekara, James Kai, Raghuveer S Makala, Peter Rabkin, George Samachisa, Jingyan Zhang
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Publication number: 20110227026Abstract: Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air brake. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element.Type: ApplicationFiled: November 9, 2010Publication date: September 22, 2011Inventors: Deepak C. Sekar, Franz Kreupl, Raghuveer Makala, Peter Rabkin, Chu-Chen Fu, Tong Zhang
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Patent number: 8023310Abstract: A nonvolatile memory cell includes a storage element, the storage element comprising a carbon material, a steering element located in series with the storage element, and a metal silicide layer located adjacent to the carbon material. A method of making a device includes forming a metal silicide over a silicon layer, forming a carbon layer over the metal silicide layer, forming a barrier layer over the carbon layer, and patterning the carbon layer, the metal silicide layer, and the silicon layer to form an array of pillars.Type: GrantFiled: January 14, 2009Date of Patent: September 20, 2011Assignee: SanDisk 3D LLCInventors: Chu-Chen Fu, Tanmay Kumar, Er-Xuan Ping, Huiwan Xu
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Publication number: 20110133151Abstract: A method of forming a reversible resistance-switching metal-insulator-metal structure is provided, the method including forming a first non-metallic conducting layer, forming a non-conducting layer above the first non-metallic conducting layer, forming a second non-metallic conducting layer above the non-conducting layer, etching the first non-metallic conducting layer, non-conducting layer and second non-metallic conducting layer to form a pillar, and disposing a carbon material layer about a sidewall of the pillar. Other aspects are also provided.Type: ApplicationFiled: December 7, 2009Publication date: June 9, 2011Applicant: SanDisk 3D LLCInventors: Yubao Li, Chu-Chen Fu, Jingyan Zhang
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Publication number: 20100176366Abstract: A nonvolatile memory cell includes a storage element, the storage element comprising a carbon material, a steering element located in series with the storage element, and a metal silicide layer located adjacent to the carbon material. A method of making a device includes forming a metal silicide over a silicon layer, forming a carbon layer over the metal silicide layer, forming a barrier layer over the carbon layer, and patterning the carbon layer, the metal silicide layer, and the silicon layer to form an array of pillars.Type: ApplicationFiled: January 14, 2009Publication date: July 15, 2010Inventors: Chu-Chen Fu, Tanmay Kumar, Er-Xuan Ping, Huiwan Xu