Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

Abstract: A non-volatile memory device implements self-convergence during the normal erase cycle through control of physical aspects, such as thickness, width, area, etc., of the dielectric layers in the gate structure as well as of the overall gate structure. Self-convergence can also be aided during the normal erase cycle by ramping the erase voltage applied to the control gate during the erase cycle.

Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

Abstract: flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.

Abstract: A non-volatile memory device implements self-convergence during the normal erase cycle through control of physical aspects, such as thickness, width, area, etc., of the dielectric layers in the gate structure as well as of the overall gate structure. Self-convergence can also be aided during the normal erase cycle by ramping the erase voltage applied to the control gate during the erase cycle.

Abstract: A flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.

Abstract: A memory array includes a buried diffusion region, a first source line that supplies electrical power to the buried diffusion region, a second source line that supplies electrical power to the buried diffusion region, a first bitline transistor having a first channel width and a second bitline transistor having a second channel width. The first bitline transistor is proximate to the first source line and is electrically coupled to a first memory cell. The first bitline transistor is disposed between the first and second source lines. The second bitline transistor is proximate to the first bitline transistor and is electrically coupled to a second memory cell. The second bitline transistor is disposed between the first and second source lines and is farther from the first source line than the first bitline transistor. The second channel width is greater than the first channel width.

Abstract: A flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.

Abstract: A memory array includes a buried diffusion region, a first source line that supplies electrical power to the buried diffusion region, a second source line that supplies electrical power to the buried diffusion region, a first bitline transistor having a first channel width and a second bitline transistor having a second channel width. The first bitline transistor is proximate to the first source line and is electrically coupled to a first memory cell. The first bitline transistor is disposed between the first and second source lines. The second bitline transistor is proximate to the first bitline transistor and is electrically coupled to a second memory cell. The second bitline transistor is disposed between the first and second source lines and is farther from the first source line than the first bitline transistor. The second channel width is greater than the first channel width.

Abstract: A flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.