Abstract: A non-volatile memory device implements self-convergence during the normal erase cycle through control of physical aspects, such as thickness, width, area, etc., of the dielectric layers in the gate structure as well as of the overall gate structure. Self-convergence can also be aided during the normal erase cycle by ramping the erase voltage applied to the control gate during the erase cycle.

Abstract: A memory management system and method. The system includes a first storage device and a processing unit. The first storage device stores an exception code excluding operation codes (op-codes) corresponding to an instruction set. The processing unit reads the exception code from the first storage device and writes it to at least one unoccupied region of a memory in an electronic device, thereby enabling the electronic device to stop program execution when the CPU fetches the exception code from the unoccupied region of the memory.

Abstract: A flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.

Abstract: A flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.

Abstract: A memory array includes a buried diffusion region, a first source line that supplies electrical power to the buried diffusion region, a second source line that supplies electrical power to the buried diffusion region, a first bitline transistor having a first channel width and a second bitline transistor having a second channel width. The first bitline transistor is proximate to the first source line and is electrically coupled to a first memory cell. The first bitline transistor is disposed between the first and second source lines. The second bitline transistor is proximate to the first bitline transistor and is electrically coupled to a second memory cell. The second bitline transistor is disposed between the first and second source lines and is farther from the first source line than the first bitline transistor. The second channel width is greater than the first channel width.

Abstract: A cell reselection method includes determining if a first C1 parameter corresponding to the serving cell is greater than a predetermined value. If the first C1 parameter is greater than the predetermined value, the method then determines if a second C2 parameter corresponding to a neighboring cell is greater than a sum of a first C2 parameter corresponding to the serving cell and a threshold value for a predetermined period. And if the second C2 parameter is greater than the sum of the first C2 parameter and the threshold for the predetermined time, cell reselection for the mobile subscriber is executed.

Abstract: A memory array includes a buried diffusion region, a first source line that supplies electrical power to the buried diffusion region, a second source line that supplies electrical power to the buried diffusion region, a first bitline transistor having a first channel width and a second bitline transistor having a second channel width. The first bitline transistor is proximate to the first source line and is electrically coupled to a first memory cell. The first bitline transistor is disposed between the first and second source lines. The second bitline transistor is proximate to the first bitline transistor and is electrically coupled to a second memory cell. The second bitline transistor is disposed between the first and second source lines and is farther from the first source line than the first bitline transistor. The second channel width is greater than the first channel width.

Abstract: A flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.

Abstract: A blade assembly is connected to a robot arm for transmission of semiconductor chips and includes a blade, a top cover, a bottom cover, and two pivot units each including a pivot arm, a first bearing, and a second bearing. Thus, the positioning flange of the mounting ring of the pivot arm is sandwiched between the first bearing and the second bearing and the inner washer is sandwiched between the inner ring of the first bearing and the inner ring of the second bearing, thereby preventing the first bearing from pressing and jamming the second bearing due to a pressing action of the urging cap, so that the pivot arm is pivotable smoothly and stably.

Abstract: A cell reselection method includes determining if a first C1 parameter corresponding to the serving cell is greater than a predetermined value. If the first C1 parameter is greater than the predetermined value, the method then determines if a second C2 parameter corresponding to a neighboring cell is greater than a sum of a first C2 parameter corresponding to the serving cell and a threshold value for a predetermined period. And if the second C2 parameter is greater than the sum of the first C2 parameter and the threshold for the predetermined time, cell reselection for the mobile subscriber is executed.

Abstract: A memory management system and method. The system includes a first storage device and a processing unit. The first storage device stores an exception code excluding operation codes (op-codes) corresponding to an instruction set. The processing unit reads the exception code from the first storage device and writes it to at least one unoccupied region of a memory in an electronic device, thereby enabling the electronic device to stop program execution when the CPU fetches the exception code from the unoccupied region of the memory.

Abstract: A USB extension system is disclosed which converts the standard USB signal into a low voltage differential signal and is installed between a USB hub or host and a USB device, and which drives the interconnecting cable with a true differential signal, i.e. a balanced signal, the problems with interference are greatly reduced. In accordance with the present invention, the standard USB signals are encoded into differential form using differential signals of different magnitudes. In one embodiment, differential signals of a “weak” magnitude are used to encode the “J” and the “K” states of the standard USB protocol, and differential signals of a “strong” magnitude are used to encode the standard “EOP” (End of Packet) USB state.

Abstract: A multi-user computer system using a communications protocol in transmitting data between a plurality of user interface units is described. The system includes a base unit, which has a bus, a processor coupled to the bus, a display device coupled to the bus, an input device also coupled to the bus, and an interface controller coupled to the bus, wherein said processor controls the operation of the base unit and processes data entered into the base unit and operates to generate output data to be displayed on the display device. The system also includes an auxiliary unit, which has a protocol interface controller, a second display device coupled to the protocol interface controller, a second input device coupled to the protocol interface controller, wherein the protocol interface controller controls the operation of the auxiliary unit and interface with the base unit in accordance with a predetermined communications protocol.

Abstract: A method of making caprolactam from aminohexanoic acid or aminohexanoate ester comprising the steps of: (a) obtaining a reactor containing at least one catalyst, the catalyst being a metal oxide having acid-base-paired active sites; (b) charging a reaction feed into the reactor, the reaction feed containing a reactant, which is either amniohexanoic acid or C.sub.1 to C.sub.12 alkyl aminohexanoate ester, and a solvent; (c) reacting the reaction feed at a reaction temperature between 140.degree. and 300.degree. C. and a reaction pressure between 10 and 100 atm, to form a product stream; and (d) separating caprolactam from the product stream.