Abstract: Provided is a patterning method including following steps. A doped polysilicon layer, a core layer, and an undoped polysilicon layer are sequentially formed on a target layer. The undoped polysilicon layer is patterned to form a polysilicon pattern. A first etching process is performed by using the polysilicon pattern as a mask to remove a portion of the core layer to form a core pattern. A second etching process is performed to remove the polysilicon pattern. An atomic layer deposition (ALD) process is performed to form a spacer material on the core pattern and the doped polysilicon layer. A portion of the spacer material is removed to form a spacer on a sidewall of the core pattern. A portion of the core pattern and an underlying doped polysilicon are removed.

Abstract: A method for forming a semiconductor structure includes providing a substrate with an opening in or on the substrate. The method further includes conformally forming a barrier layer in the opening and on the substrate and performing an implantation process to implant a dopant into the barrier layer. The method further includes conformally forming a capping layer on the barrier layer and performing an annealing process, such that the dopant diffuses into the grain boundary of the barrier layer. The method further includes removing the capping layer and filling the opening with a conductive material.

Abstract: A method for forming a semiconductor structure is provided. The method includes providing a semiconductor substrate with a plurality of floating gates on it, and an isolation structure between the floating gates. The method includes performing a first etching process to recess the isolation structure and to form an opening between the floating gates to expose a portion of the sidewalls of the floating gates. The method includes conformally forming a liner in the opening. The method includes performing an ion implantation process to implant a dopant into the isolation structure below the liner. The method includes performing a second etching process to remove the liner and a portion of the isolation structure below the liner, thereby giving the bottom portion of the opening a tapered profile.

Abstract: Provided is a patterning method including following steps. A doped polysilicon layer, a core layer, and an undoped polysilicon layer are sequentially formed on a target layer. The undoped polysilicon layer are patterned to form a polysilicon pattern. A first etching process is performed by using the polysilicon pattern as a mask to remove a portion of the core layer to form a core pattern. A second etching process is performed to remove the polysilicon pattern. An atomic layer deposition (ALD) process is performed to form a spacer material on the core pattern and the doped polysilicon layer. A portion of the spacer material is removed to form a spacer on a sidewall of the core pattern. A portion of the core pattern and an underlying doped polysilicon are removed.

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a tunneling oxide layer, a floating gate, a dielectric layer, and a control gate. The tunneling oxide layer is formed on a substrate. The floating gate is formed on the tunneling oxide layer, and includes a first polysilicon layer, a second polysilicon layer, and a nitrogen dopant. A grain of the first polysilicon layer has a first grain size, and a grain of the second polysilicon layer has a second grain size that is greater than the first grain size. The nitrogen dopant is formed in interstices between the grains of the first polysilicon layer. The dielectric layer includes a first nitride film, an oxide layer, a nitride layer, and an oxide layer conformally formed on the floating gate. The control gate is formed on the dielectric layer.

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a tunneling oxide layer, a floating gate, a dielectric layer, and a control gate. The tunneling oxide layer is formed on a substrate. The floating gate is formed on the tunneling oxide layer, and includes a first polysilicon layer, a second polysilicon layer, and a nitrogen dopant. A grain of the first polysilicon layer has a first grain size, and a grain of the second polysilicon layer has a second grain size that is greater than the first grain size. The nitrogen dopant is formed in interstices between the grains of the first polysilicon layer. The dielectric layer includes a first nitride film, an oxide layer, a nitride layer, and an oxide layer conformally formed on the floating gate. The control gate is formed on the dielectric layer.

Abstract: A non-volatile memory device and its manufacturing method are provided. The non-volatile memory device includes a tunneling oxide layer, a floating gate, a dielectric layer, and a control gate. The tunneling oxide layer is formed on a substrate. The floating gate is formed on the tunneling oxide layer, and includes a first polysilicon layer, a second polysilicon layer, and a nitrogen dopant. A grain of the first polysilicon layer has a first grain size, and a grain of the second polysilicon layer has a second grain size that is greater than the first grain size. The nitrogen dopant is formed in interstices between the grains of the first polysilicon layer. The dielectric layer includes a first nitride film, an oxide layer, a nitride layer, and an oxide layer conformally formed on the floating gate. The control gate is formed on the dielectric layer.

Abstract: A non-volatile memory device and its manufacturing method are provided. The non-volatile memory device includes a tunneling oxide layer, a floating gate, a dielectric layer, and a control gate. The tunneling oxide layer is formed on a substrate. The floating gate is formed on the tunneling oxide layer, and includes a first polysilicon layer, a second polysilicon layer, and a nitrogen dopant. A grain of the first polysilicon layer has a first grain size, and a grain of the second polysilicon layer has a second grain size that is greater than the first grain size. The nitrogen dopant is formed in interstices between the grains of the first polysilicon layer. The dielectric layer includes a first nitride film, an oxide layer, a nitride layer, and an oxide layer conformally formed on the floating gate. The control gate is formed on the dielectric layer.