Abstract: An electronic circuit for online monitoring a clock signal is provided. The electronic circuit includes a period-to-pulse converter, a pulse-shrinking block and an encoder. The period-to-pulse converter receives the clock signal outputted by a phase-locked loop, and converts each of a plurality of clock period samples of the clock signal to generate a pulse-train signal having a plurality of pulses. The pulse-shrinking block receives the plurality of pulses of the pulse-train signal, and generates a plurality of catch bits by shrinking the plurality of pulses of the pulse-train signal. The encoder outputs a minimum code denoting a minimum clock period of the clock signal and a maximum code denoting a maximum clock period of the clock signal according to the plurality of catch bits. The electronic circuit subtracts the maximum code and the minimum code to generate a peak-to-peak jitter amount code.

Abstract: An electronic circuit for online monitoring a clock signal is provided. The electronic circuit includes a period-to-pulse converter, a pulse-shrinking block and an encoder. The period-to-pulse converter receives the clock signal outputted by a phase-locked loop, and converts each of a plurality of clock period samples of the clock signal to generate a pulse-train signal having a plurality of pulses. The pulse-shrinking block receives the plurality of pulses of the pulse-train signal, and generates a plurality of catch bits by shrinking the plurality of pulses of the pulse-train signal. The encoder outputs a minimum code denoting a minimum clock period of the clock signal and a maximum code denoting a maximum clock period of the clock signal according to the plurality of catch bits. The electronic circuit subtracts the maximum code and the minimum code to generate a peak-to-peak jitter amount code.

Abstract: The disclosure provides a semiconductor package structure, including a substrate having a front side and a back side, a first insulating layer disposed on the front side of the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second portion of the metal layer spaced apart by a second insulating layer. An associated semiconductor packaging method and another semiconductor package structure are also disclosed.

Abstract: The present disclosure provides a method for preparing a semiconductor package having a standard size from a die having a size smaller than the standard size. The method includes: providing a wafer; forming a die on the wafer, wherein the die has a size smaller than one-half of a standard size 0201; dicing the die from the wafer; encapsulating the die to form an encapsulated die; and singulating the encapsulated die to form a semiconductor package having a size equal to or larger than the standard size 0201.

Abstract: The present disclosure provides a method for preparing a semiconductor package having a standard size from a die having a size smaller than the standard size. The method includes: providing a wafer; forming a die on the wafer, wherein the die has a size smaller than one-half of a standard size 0201; dicing the die from the wafer; encapsulating the die to form an encapsulated die; and singulating the encapsulated die to form a semiconductor package having a size equal to or larger than the standard size 0201.

Abstract: The present disclosure provides a semiconductor package having a size equal to or larger than standard size 0201. The semiconductor package includes a die and a packing member. The size of the die is smaller than one-half of the standard size 0201, and the packing member encapsulates the die.

Abstract: The disclosure provides a semiconductor package structure, including a substrate having a front side and a back side, a first insulating layer disposed on the front side of the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second. portion of the metal layer spaced apart by a second insulating layer. An associated semiconductor packaging method and another semiconductor package structure are also disclosed.

Abstract: The disclosure provides a semiconductor package structure, including a substrate having a front side and a back side, a first insulating layer disposed on the front side of the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second portion of the metal layer spaced apart by a second insulating layer. An associated semiconductor packaging method and another semiconductor package structure are also disclosed.

Abstract: The disclosure provides a semiconductor package structure, including a substrate having a front side and a back side, a first insulating layer disposed on the front side of the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second portion of the metal layer spaced apart by a second insulating layer. An associated semiconductor packaging method and another semiconductor package structure are also disclosed.

Abstract: A semiconductor package structure includes a chip unit, a package unit and an electrode unit. The chip unit includes at least one semiconductor chip. The semiconductor chip has an upper surface, a lower surface, and a surrounding peripheral surface connected between the upper and the lower surfaces, and the semiconductor chip has a first conductive pad and a second conductive pad disposed on the lower surface thereof. The package unit includes a package body covering the upper surface and the surrounding peripheral surface of the semiconductor chip. The package body has a first lateral portion and a second lateral portion respectively formed on two opposite lateral sides thereof. The electrode unit includes a first electrode structure covering the first lateral portion and a second electrode structure covering the second lateral portion. The first and the second electrode structures respectively electrically contact the first and the second conductive pads.

Abstract: A semiconductor package structure includes a chip unit, a package unit and an electrode unit. The chip unit includes at least one semiconductor chip. The semiconductor chip has an upper surface, a lower surface, and a surrounding peripheral surface connected between the upper and the lower surfaces, and the semiconductor chip has a first conductive pad and a second conductive pad disposed on the lower surface thereof. The package unit includes a package body covering the upper surface and the surrounding peripheral surface of the semiconductor chip. The package body has a first lateral portion and a second lateral portion respectively formed on two opposite lateral sides thereof. The electrode unit includes a first electrode structure covering the first lateral portion and a second electrode structure covering the second lateral portion. The first and the second electrode structures respectively electrically contact the first and the second conductive pads.