Patents by Inventor Chu-Hsin Liang

Chu-Hsin Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088132
    Abstract: An integrated circuit structure includes a sub-fin having (i) a first portion including a p-type dopant and (ii) a second portion including an n-type dopant. A first body of semiconductor material is above the first portion of the sub-fin, and a second body of semiconductor material is above the second portion of the sub-fin. In an example, the first portion of the sub-fin and the second portion of the sub-fin are in contact with each other, to form a PN junction of a diode. For example, the first portion of the sub-fin is part of an anode of the diode, and wherein the second portion of the sub-fin is part of a cathode of the diode.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Nicholas A. Thomson, Kalyan C. Kolluru, Ayan Kar, Chu-Hsin Liang, Benjamin Orr, Biswajeet Guha, Brian Greene, Chung-Hsun Lin, Sabih U. Omar, Sameer Jayanta Joglekar
  • Publication number: 20230420443
    Abstract: Integrated circuit (IC) devices with diodes formed in a subfin between a support structure of an IC device and one or more nanoribbon stacks are disclosed. To alleviate challenges of limited semiconductor cross-section provided by the subfin, etch depths in the subfin (i.e., depths of recesses in the subfin formed as a part of forming the diodes) are selectively optimized and varied. Deeper recesses are made in subfin portions at which diode terminals (e.g., anodes and cathodes) are formed, to increase the semiconductor cross-section in those portions, thus providing improved subfin contacts. Shallower recesses (or no recesses) are made in subfin portion between the diode terminals, to increase subfin retention. Thus, subfin diodes may be provided in a manner that enables improved diode conductance and/or improved current carrying capabilities while advantageously using substantially the same etch processes as those used for forming nanoribbon-based transistors elsewhere in the IC device.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Nicholas A. Thomson, Ayan Kar, Kalyan C. Kolluru, Benjamin John Orr, Chu-Hsin Liang, Biswajeet Guha, Saptarshi Mandal, Brian Greene, Sameer Jayanta Joglekar, Chung-Hsun Lin, Mauro J. Kobrinsky
  • Patent number: 7838959
    Abstract: Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one radio frequency (RF) circuit or a portion thereof is disposed in at least one of the plurality of rows of the array of the plurality of devices.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: November 23, 2010
    Assignee: Infineon Technologies AG
    Inventors: Uwe Paul Schroeder, Chu-Hsin Liang
  • Publication number: 20090189195
    Abstract: Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one radio frequency (RF) circuit or a portion thereof is disposed in at least one of the plurality of rows of the array of the plurality of devices.
    Type: Application
    Filed: January 29, 2008
    Publication date: July 30, 2009
    Inventors: Uwe Paul Schroeder, Chu-Hsin Liang