Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple semiconductor nanostructures, and the semiconductor nanostructures include a first semiconductor material. The semiconductor device structure also includes multiple epitaxial structures extending from edges of the semiconductor nanostructures. The epitaxial structures include a second semiconductor material that is different than the first semiconductor material. The semiconductor device structure further includes a gate stack wrapped around the semiconductor nanostructures.

Abstract: An electronic apparatus including a compression molding board and a connection pad is provided. The compression molding board has a device bonding area and a bending area formed by compression molding. The device bonding area is different from the bending area. The connection pad is disposed on the device bonding area of the compression molding board.

Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.

Abstract: The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) providing a first layout including a plurality of cells placed therein; (b) generating a second layout by performing a first set of calculations on the first layout such that cell congestions in the first layout is eliminated from the second layout; (c) generating a third layout by performing a second set of calculations on the second layout such that the total wire length of the third layout is less than that of the second layout; and (d) iterating the operations (b) and (c) until a target layout conforming a convergence criterion.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming an epitaxial stack over a substrate, the epitaxial stack comprising alternating sacrificial layers and channel layers; patterning the epitaxial stack into a first fin and a second fin; forming a dielectric wall between the first and second fins; forming a dielectric structure surrounding the first and second fins; depositing a protection layer over the first and second fins; after depositing the protection layer, etching back the dielectric structure to exposes sidewalls of the sacrificial layers; and replacing the sacrificial layers with a gate structure.

Abstract: The present disclosure provides a method for fabricating a semiconductor structure, including bonding a capping substrate over a sensing substrate, forming a through hole traversing the capping substrate, forming a dielectric layer over the capping substrate under a first vacuum level, and forming a metal layer over the dielectric layer under a second vacuum level, wherein the second vacuum level is higher than the first vacuum level.

Abstract: A part is adapted to be used in a semiconductor processing equipment. The part includes a substrate and a protective coating. The protective coating covers at least a part of the substrate, is made of silicon carbide, and has an atomic ratio of carbon in the protective coating increases in a direction away from the substrate while an atomic ratio of silicon in the protective coating decreases in the direction. The atomic ratio of silicon in the protective coating is larger than that of the carbon near the substrate, and the atomic ratio of silicon in the protective coating is smaller than that of carbon near the outer surface of the protective coating. A method for making the part is also provided.

Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.

Abstract: A plasma monitoring device including at least one first cathode, at least one second cathode, a first collimator group, a first mass flow controller group, and a plasma emission monitor is disclosed. The first cathode has a first target and provides a first plasma. The second cathode has a second target and provides a second plasma. The first collimator group is disposed corresponding to the first cathode to detect a first spectrum of the first plasma. The first mass flow controller group provides gas to the first cathode and the second cathode through a first gas supply pipe group and a second gas supply pipe group. The plasma emission monitor adjusts a flow rate of the gas provided by the first mass flow controller group according to the first spectrum of the first plasma. The first target and the second target are the same. A total number of collimator groups is less than a total number of cathodes.

Abstract: The present invention discloses that a plasma aerosol device includes a gas tunnel, a dielectric barrier discharge module, and a liquid tunnel. The invention uses a mechanism similar to a dielectric barrier discharge (DBD) electrode system, thus to enable generating a plasma active water mist which riches in free radicals such as reactive nitrogen species (RNS) and reactive oxygen species (ROS). Therefore, this invention is able to be used in medical, sterilization, agriculture and preservation industries.

Abstract: The invention discloses a flexible transparent conductive composite film and the manufacturing method thereof. The aforementioned flexible transparent conductive composite film is formed by depositing the first target material and the second target material in an alternating manner by HiPIMS. Therefore, the post-anneal step of the traditional method can be omitted, and the manufacturing efficiency of the flexible transparent conductive composite films is significantly improved.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

Abstract: The present invention discloses an organic polymer film and a manufacturing method thereof. The organic polymer film is mainly manufactured by the following steps. Firstly, the step (A) provides a xylene precursor and a substrate, and the step (B) places the substrate inside of a plasma equipment. After that, the step (C) evacuates the plasma equipment while introducing a carrier gas which carries vapor of the xylene precursor, and the step (D) turns on a pulse power supply system of the plasma equipment, generating a short pulse for plasma ignition. Finally, the step (E) forms the organic polymer film on the substrate. In the aforementioned steps, the frequency of the short pulse plasma is between 1 Hz˜10,000 Hz, and the pulse period of the short pulse plasma is between 1 ?s˜60 ?s.

Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first t

Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, depositing a second dielectric layer over the first dielectric layer, recessing the first dielectric layer to define a dummy fin between the first semiconductor fin and the second semiconductor fin, forming a cap layer over top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, wherein the forming the cap layer comprises depositing the cap layer in a furnace at process temperatures higher than a first temperature, and lowering the temperature of the furnace, wherein during the lowering the temperature of the furnace, the pressure in the furnace is raised to and maintained at 10 torr or higher until the temperature of the furnace drops below the first temperature.

Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, depositing a second dielectric layer over the first dielectric layer, recessing the first dielectric layer to define a dummy fin between the first semiconductor fin and the second semiconductor fin, forming a cap layer over top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, wherein the forming the cap layer comprises depositing the cap layer in a furnace at process temperatures higher than a first temperature, and lowering the temperature of the furnace, wherein during the lowering the temperature of the furnace, the pressure in the furnace is raised to and maintained at 10 torr or higher until the temperature of the furnace drops below the first temperature.

Abstract: A fan module is disposed with a fan mechanism having a fixing portion. The fixing portion has a first surface, a second surface, and a perforation passing through the first and the second surface, wherein the first surface and the second surface face opposite directions. A connector is disposed in the perforation and is electrically connected to a wire set which is adapted to transmit a signal or electric power. A shell of the connector includes a body for passing through the perforation and a protruding portion protruding away from a circumference of the body and abutting against the first surface of the fixing portion. The restricting member is detachably engaged with the fixing portion and the connector to clamp the protruding portion and the fixing portion by two restricting plates of the restricting member. With such design, the fan module could be installed to a site via the connector to achieve positioning and electrical connection once.

Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, depositing a second dielectric layer over the first dielectric layer, recessing the first dielectric layer to define a dummy fin between the first semiconductor fin and the second semiconductor fin, forming a cap layer over top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, wherein the forming the cap layer comprises depositing the cap layer in a furnace at process temperatures higher than a first temperature, and lowering the temperature of the furnace, wherein during the lowering the temperature of the furnace, the pressure in the furnace is raised to and maintained at 10 torr or higher until the temperature of the furnace drops below the first temperature.