Patents by Inventor CHU LIANG

CHU LIANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240420951
    Abstract: A part is adapted to be used in a semiconductor processing equipment. The part includes a substrate and a protective coating. The protective coating covers at least a part of the substrate, is made of silicon carbide, and has an atomic ratio of carbon in the protective coating increases in a direction away from the substrate while an atomic ratio of silicon in the protective coating decreases in the direction. The atomic ratio of silicon in the protective coating is larger than that of the carbon near the substrate, and the atomic ratio of silicon in the protective coating is smaller than that of carbon near the outer surface of the protective coating. A method for making the part is also provided.
    Type: Application
    Filed: August 26, 2024
    Publication date: December 19, 2024
    Inventors: Chang-Ho YU, Yao-Kuang Yang, Ping-Yen Hsieh, Ying-Hung Chen, Chu-Liang Ho
  • Patent number: 12170228
    Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: December 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Yao Chen, Pin-Chu Liang, Hsueh-Chang Sung, Pei-Ren Jeng, Yee-Chia Yeo
  • Patent number: 12164854
    Abstract: The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) placing a plurality of cells in a first layout; (b) generating a second layout by performing a first set of calculations on the first layout such that a total wire length of the second layout is less than that of the first layout; (c) generating a third layout by performing a second set of calculations on the second layout such that cell congestions in the second layout is eliminated from the third layout; (d) generating a fourth layout by performing a third set of calculations on the third layout such that the total wire length of the fourth layout is less than that of the third layout; and (e) iterating the operations (c) and (d) until a target layout conforms to a convergence criterion.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ting-Chi Wang, Wai-Kei Mak, Kuan-Yu Chen, Hsiu-Chu Hsu, Hsuan-Han Liang, Sheng-Hsiung Chen
  • Publication number: 20240363722
    Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Ting CHEN, Tsai-Jung Ho, Tsung-Han Ko, Tetsuji Ueno, Yahru Cheng, Chen-Han Wang, Keng-Chu Lin, Shuen-Shin Liang, Tsu-Hsiu Perng
  • Publication number: 20240360720
    Abstract: A cord divider is positioned on both sides of the cord winder of the control box of a cordless window curtain. Each cord divider is equipped with protrusions and crosspieces. When the cords are pulled out from the cord divider, the cords do not tangle or knot. The cords are wound up on the driving gear set, and the driving cord device prevents the cords from overlapping and causing uneven heights on both sides of the curtain. The use of cylinders in the cord dividers prevents excessive friction of the cords during use. There is no need to change the current cooperation way between the cords and the cord winder.
    Type: Application
    Filed: July 12, 2023
    Publication date: October 31, 2024
    Inventors: WEN YING LIANG, Sheng Ying HSU, Chien Chih HUANG, Wu Chung NIEN, Ming Chu CHIANG, Wei Ming SHIH
  • Publication number: 20240363319
    Abstract: A plasma monitoring device including at least one first cathode, at least one second cathode, a first collimator group, a first mass flow controller group, and a plasma emission monitor is disclosed. The first cathode has a first target and provides a first plasma. The second cathode has a second target and provides a second plasma. The first collimator group is disposed corresponding to the first cathode to detect a first spectrum of the first plasma. The first mass flow controller group provides gas to the first cathode and the second cathode through a first gas supply pipe group and a second gas supply pipe group. The plasma emission monitor adjusts a flow rate of the gas provided by the first mass flow controller group according to the first spectrum of the first plasma. The first target and the second target are the same. A total number of collimator groups is less than a total number of cathodes.
    Type: Application
    Filed: July 18, 2023
    Publication date: October 31, 2024
    Applicant: Dah Young Vacuum Equipment Co., Ltd.
    Inventors: Tzu-Hou Chan, Ching-Yen Lin, Chu-Liang Ho, Ping-Yen Hsieh, Ying-Hung Chen
  • Publication number: 20240355733
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first nitride-containing layer on a side of a carrier substrate, first semiconductor devices thermally coupled to the first nitride-containing layer, a first interconnect structure physically and electrically coupled to first sides of the first semiconductor devices, and a first metal-containing dielectric layer bonding the first nitride-containing layer to the first interconnect structure. A thermal conductivity of the first nitride-containing layer is greater than a thermal conductivity of the first metal-containing dielectric layer.
    Type: Application
    Filed: April 20, 2023
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zheng-Yong Liang, Wei-Ting Yeh, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20240355805
    Abstract: Provided is a method of forming a semiconductor structure including: bonding a device wafer onto a carrier wafer; forming a support structure between an edge of the device wafer and an edge of the carrier wafer, wherein the support structure surrounds a device layer of the device wafer along a closed path; removing a substrate and a portion of a bonding dielectric layer of the device wafer from a backside of the device wafer to expose the support structures while the support structure is in place; and removing the support structure through an acid etchant.
    Type: Application
    Filed: April 21, 2023
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ting Yeh, Zheng-Yong Liang, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20240355741
    Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.
    Type: Application
    Filed: July 1, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuen-Shin LIANG, Chun-I TSAI, Chih-Wei CHANG, Chun-Hsien HUANG, Hung-Yi HUANG, Keng-Chu LIN, Ken-Yu CHANG, Sung-Li WANG, Chia-Hung CHU, Hsu-Kai CHANG
  • Patent number: 12122088
    Abstract: A production line for producing components to a high standard of cleanliness and sealed and protected in that state includes a loading device, a cleaning device, a detecting device, a pasting device, a heat-sealing device, a packing device, and transfer devices of the production line. The production line automatically processes the components for obtaining components with the high cleanliness. By the processes of protective film pasting, heat-sealing, and packing, the components may be further protected from subsequent pollution. A method for producing components with a high cleanliness applied to the production line is also disclosed.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: October 22, 2024
    Assignee: Fulian Yuzhan Precision Technology Co., Ltd
    Inventors: Jian-Wen Gao, Ting-Ting Li, Chu-Hui Wu, Ai-Jun Tang, Hui Wang, Shi Chen, Bo Yang, Feng Zhang, Kun-Liang Lin, Jian-Gang Zhang
  • Publication number: 20240347479
    Abstract: A semiconductor package includes a package substrate having a top surface and an opposing bottom surface. The package substrate includes a top build-up wiring layer and an upper dielectric layer covering the top build-up wiring layer. A semiconductor device and a passive component are mounted on the top surface of the package substrate in a side-by-side manner. A molding compound encapsulates the semiconductor device and the passive component on the top surface of the package substrate. A cavity is disposed between the passive component and the top surface of the package substrate.
    Type: Application
    Filed: March 20, 2024
    Publication date: October 17, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chu-Chia Chang, Pei-Haw Tsao, Peng-Yu Huang, Yu-Liang Hsiao, Wei-Fan Chen
  • Patent number: 12120605
    Abstract: A wireless communication method of a wireless communication device is disclosed, wherein the wireless communication method includes the steps of: establishing a link with a first access point, and obtaining a BSSID list of a plurality of access points of a self-organizing network from the first access point of the SON during a link process; determining at least one candidate access point from the plurality of access point according to the BSSID list; and selecting one of the at least one candidate access point to establish a link.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: October 15, 2024
    Assignee: Wistron NeWeb Corporation
    Inventors: Hao-Ming Liang, Chui-Chu Cheng, Chih-Wei Chung
  • Publication number: 20240337150
    Abstract: A method for forming a honeycomb curtain and includes a weaving process, a fixing process, a gluing process, a stacking process and a cutting process. The honeycomb curtain includes multiple netted tubes, and each netted tube includes an upper portion and a lower portion. The central portion of each of the upper and lower portions is woven to form a tight-woven structure. Two sides of each of the central portions are woven to form a sparse-woven structure to form the upper portion to be a breathable first semi-transparent strip and to form the lower portion to be a second semi-transparent strip. The outer corner of each of the upper and lower portions are woven to form another tight-woven structure. The central portions of each of the netted tubes are applied with glue on respective outer face thereof. The netted tubes are stacked and pressed to form a layered structure.
    Type: Application
    Filed: November 28, 2023
    Publication date: October 10, 2024
    Inventors: WEN YING LIANG, Sheng Ying HSU, Chien Chih HUANG, Wu Chung NIEN, Ming Chu CHIANG, Wei Ming SHIH
  • Patent number: 12112974
    Abstract: Examples of a technique for forming a dielectric material for an integrated circuit are provided herein. In an example, an integrated circuit workpiece is received that includes a recess. A first dielectric precursor is deposited in the recess. The first dielectric precursor includes a non-semiconductor component. A second dielectric precursor is deposited in the recess on the first dielectric precursor, and an annealing process is performed such that a portion of the non-semiconductor component of the first dielectric precursor diffuses into the second dielectric precursor. The non-semiconductor component may include oxygen, and the annealing process may be performed in one of a vacuum or an inert gas environment.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: October 8, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tang Peng, Shuen-Shin Liang, Keng-Chu Lin, Teng-Chun Tsai
  • Patent number: 12094952
    Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: September 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Ting Chen, Chen-Han Wang, Keng-Chu Lin, Shuen-Shin Liang, Tsu-Hsiu Perng, Tsai-Jung Ho, Tsung-Han Ko, Tetsuji Ueno, Yahru Cheng
  • Patent number: 12074110
    Abstract: A method for forming a semiconductor device includes receiving a first bonded to a second substrate by a dielectric layer, wherein a conductive layer is disposed in the dielectric layer and a cavity is formed between the first substrate, the second substrate and the dielectric layer; forming a via opening in the second substrate to expose the conductive layer and a vent hole in the substrate to couple to the cavity; forming a first buffer layer covering sidewalls of the via opening and a second buffer layer covering sidewalls of the vent hole; and forming a connecting structure in the via opening and a sealing structure to seal the vent hole.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ching-Kai Shen, Yi-Chuan Teng, Wei-Chu Lin, Hung-Wei Liang, Jung-Kuo Tu
  • Publication number: 20240282761
    Abstract: A carrier structure and methods of forming and using the same are described. In some embodiments, the method includes forming one or more devices over a substrate, forming a first interconnect structure over the one or more devices, and bonding the first interconnect structure to a carrier structure. The carrier structure includes a semiconductor substrate, a release layer, and a first dielectric layer, and the release layer includes a metal nitride. The method further includes flipping over the one or more devices so the carrier structure is located at a bottom, performing backside processes, flipping over the one or more devices so the carrier structure is located at a top, and exposing the carrier structure to IR lights. Portions of the release layer are separated from the first dielectric layer.
    Type: Application
    Filed: February 22, 2023
    Publication date: August 22, 2024
    Inventors: Zheng Yong Liang, Wei-Ting Yeh, Jyh-Cherng Sheu, Yu-Yun Peng, Keng-Chu Lin
  • Patent number: 12069792
    Abstract: The present invention discloses that a plasma aerosol device includes a gas tunnel, a dielectric barrier discharge module, and a liquid tunnel. The invention uses a mechanism similar to a dielectric barrier discharge (DBD) electrode system, thus to enable generating a plasma active water mist which riches in free radicals such as reactive nitrogen species (RNS) and reactive oxygen species (ROS). Therefore, this invention is able to be used in medical, sterilization, agriculture and preservation industries.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: August 20, 2024
    Assignee: FENG CHIA UNIVERSITY
    Inventors: Guan-Heng Lyu, Ying-Hung Chen, Ping-Yen Hsieh, Tsung-Han Chen, Chu-Liang Ho
  • Patent number: 12057397
    Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: August 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuen-Shin Liang, Chun-I Tsai, Chih-Wei Chang, Chun-Hsien Huang, Hung-Yi Huang, Keng-Chu Lin, Ken-Yu Chang, Sung-Li Wang, Chia-Hung Chu, Hsu-Kai Chang
  • Patent number: 12051521
    Abstract: The invention discloses a flexible transparent conductive composite film and the manufacturing method thereof. The aforementioned flexible transparent conductive composite film is formed by depositing the first target material and the second target material in an alternating manner by HiPIMS. Therefore, the post-anneal step of the traditional method can be omitted, and the manufacturing efficiency of the flexible transparent conductive composite films is significantly improved.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: July 30, 2024
    Assignee: FENG CHIA UNIVERSITY
    Inventors: Jia-Lin Syu, Ying-Hung Chen, Ping-Yen Hsieh, Chu-Liang Ho