Patents by Inventor CHU LIANG

CHU LIANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240178120
    Abstract: An integrated fan-out package includes a first redistribution structure, a die, conductive structures, an encapsulant, and a second redistribution structure. The first redistribution structure has first regions and a second region surrounding the first regions. A metal density in the first regions is smaller than a metal density in the second region. The die is disposed over the first redistribution structure. The conductive structures are disposed on the first redistribution structure to surround the die. Vertical projections of the conductive structures onto the first redistribution structure fall within the first regions of the first redistribution structure. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant, the die, and the conductive structures.
    Type: Application
    Filed: February 8, 2023
    Publication date: May 30, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Tzu-Sung Huang, Wei-Kang Hsieh, Hao-Yi Tsai, Ming-Hung Tseng, Tsung-Hsien Chiang, Yen-Liang Lin, Chu-Chun Chueh
  • Publication number: 20240170323
    Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mrunal Abhijith KHADERBAD, Ko-Feng Chen, Zheng-Yong Liang, Chen-Han Wang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20240162083
    Abstract: The present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls oppose each other. The method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. The second dielectric material and the first and second sidewalls entrap a pocket of air. The method also includes performing a treatment process on the second dielectric material.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Chen-Han WANG, Keng-Chu LIN, Tetsuji UENO, Ting-Ting CHEN
  • Publication number: 20240145581
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Wen CHIU, Yi Che CHAN, Lun-Kuang TAN, Zheng-Yang PAN, Cheng-Po CHAU, Pin-Chu LIANG, Hung-Yao CHEN, De-Wei YU, Yi-Cheng LI
  • Patent number: 11974071
    Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.
    Type: Grant
    Filed: August 21, 2022
    Date of Patent: April 30, 2024
    Assignee: MEDIATEK INC.
    Inventors: Kang-Yi Fan, Chin-Wen Liang, Chang-Chu Liu, Sheng-Hsiang Chang, You-Min Yeh
  • Patent number: 11969752
    Abstract: The present invention discloses an organic polymer film and a manufacturing method thereof. The organic polymer film is mainly manufactured by the following steps. Firstly, the step (A) provides a xylene precursor and a substrate, and the step (B) places the substrate inside of a plasma equipment. After that, the step (C) evacuates the plasma equipment while introducing a carrier gas which carries vapor of the xylene precursor, and the step (D) turns on a pulse power supply system of the plasma equipment, generating a short pulse for plasma ignition. Finally, the step (E) forms the organic polymer film on the substrate. In the aforementioned steps, the frequency of the short pulse plasma is between 1 Hz˜10,000 Hz, and the pulse period of the short pulse plasma is between 1 ?s˜60 ?s.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: April 30, 2024
    Assignee: FENG CHIA UNIVERSITY
    Inventors: Ping-Yen Hsieh, Xuan-Xuan Chang, Ying-Hung Chen, Chu-Liang Ho
  • Patent number: 11948840
    Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Yao Chen, Pin-Chu Liang, Hsueh-Chang Sung, Pei-Ren Jeng, Yee-Chia Yeo
  • Publication number: 20240105848
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple semiconductor nanostructures, and the semiconductor nanostructures include a first semiconductor material. The semiconductor device structure also includes multiple epitaxial structures extending from edges of the semiconductor nanostructures. The epitaxial structures include a second semiconductor material that is different than the first semiconductor material. The semiconductor device structure further includes a gate stack wrapped around the semiconductor nanostructures.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuen-Shin LIANG, Pang-Yen TSAI, Keng-Chu LIN, Sung-Li WANG, Pinyen LIN
  • Patent number: 11942358
    Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Ko-Feng Chen, Zheng-Yong Liang, Chen-Han Wang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
  • Patent number: 11929327
    Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Inc.
    Inventors: Hsu-Kai Chang, Keng-Chu Lin, Sung-Li Wang, Shuen-Shin Liang, Chia-Hung Chu
  • Patent number: 11901442
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Wen Chiu, Yi Che Chan, Lun-Kuang Tan, Zheng-Yang Pan, Cheng-Po Chau, Pin-Chu Liang, Hung-Yao Chen, De-Wei Yu, Yi-Cheng Li
  • Publication number: 20230402326
    Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first t
    Type: Application
    Filed: August 8, 2023
    Publication date: December 14, 2023
    Inventors: Hung-Yao Chen, Pin-Chu Liang, Hsueh-Chang Sung, Pei-Ren Jeng, Yee-Chia Yeo
  • Publication number: 20230317831
    Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, depositing a second dielectric layer over the first dielectric layer, recessing the first dielectric layer to define a dummy fin between the first semiconductor fin and the second semiconductor fin, forming a cap layer over top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, wherein the forming the cap layer comprises depositing the cap layer in a furnace at process temperatures higher than a first temperature, and lowering the temperature of the furnace, wherein during the lowering the temperature of the furnace, the pressure in the furnace is raised to and maintained at 10 torr or higher until the temperature of the furnace drops below the first temperature.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 5, 2023
    Inventors: Pin Chu Liang, Hung-Yao Chen, Pei-Ren Jeng
  • Patent number: 11710781
    Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, depositing a second dielectric layer over the first dielectric layer, recessing the first dielectric layer to define a dummy fin between the first semiconductor fin and the second semiconductor fin, forming a cap layer over top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, wherein the forming the cap layer comprises depositing the cap layer in a furnace at process temperatures higher than a first temperature, and lowering the temperature of the furnace, wherein during the lowering the temperature of the furnace, the pressure in the furnace is raised to and maintained at 10 torr or higher until the temperature of the furnace drops below the first temperature.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pin Chu Liang, Hung-Yao Chen, Pei-Ren Jeng
  • Publication number: 20230178942
    Abstract: A fan module is disposed with a fan mechanism having a fixing portion. The fixing portion has a first surface, a second surface, and a perforation passing through the first and the second surface, wherein the first surface and the second surface face opposite directions. A connector is disposed in the perforation and is electrically connected to a wire set which is adapted to transmit a signal or electric power. A shell of the connector includes a body for passing through the perforation and a protruding portion protruding away from a circumference of the body and abutting against the first surface of the fixing portion. The restricting member is detachably engaged with the fixing portion and the connector to clamp the protruding portion and the fixing portion by two restricting plates of the restricting member. With such design, the fan module could be installed to a site via the connector to achieve positioning and electrical connection once.
    Type: Application
    Filed: September 19, 2022
    Publication date: June 8, 2023
    Applicant: ACCTON TECHNOLOGY CORPORATION
    Inventor: TA-CHU LIANG
  • Publication number: 20230064078
    Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, depositing a second dielectric layer over the first dielectric layer, recessing the first dielectric layer to define a dummy fin between the first semiconductor fin and the second semiconductor fin, forming a cap layer over top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, wherein the forming the cap layer comprises depositing the cap layer in a furnace at process temperatures higher than a first temperature, and lowering the temperature of the furnace, wherein during the lowering the temperature of the furnace, the pressure in the furnace is raised to and maintained at 10 torr or higher until the temperature of the furnace drops below the first temperature.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Pin Chu Liang, Hung-Yao Chen, Pei-Ren Jeng
  • Publication number: 20230064844
    Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Hung-Yao Chen, Pin-Chu Liang, Hsueh-Chang Sung, Pei-Ren Jeng, Yee-Chia Yeo
  • Publication number: 20220193719
    Abstract: The present invention discloses an organic polymer film and a manufacturing method thereof. The organic polymer film is mainly manufactured by the following steps. Firstly, the step (A) provides a xylene precursor and a substrate, and the step (B) places the substrate inside of a plasma equipment. After that, the step (C) evacuates the plasma equipment while introducing a carrier gas which carries vapor of the xylene precursor, and the step (D) turns on a pulse power supply system of the plasma equipment, generating a short pulse for plasma ignition. Finally, the step (E) forms the organic polymer film on the substrate. In the aforementioned steps, the frequency of the short pulse plasma is between 1 Hz˜10,000 Hz, and the pulse period of the short pulse plasma is between 1 ?s˜60 ?s.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 23, 2022
    Inventors: PING-YEN HSIEH, XUAN-XUAN CHANG, YING-HUNG CHEN, CHU-LIANG HO
  • Publication number: 20220199282
    Abstract: The invention discloses a flexible transparent conductive composite film and the manufacturing method thereof. The aforementioned flexible transparent conductive composite film is formed by depositing the first target material and the second target material in an alternating manner by HiPIMS. Therefore, the post-anneal step of the traditional method can be omitted, and the manufacturing efficiency of the flexible transparent conductive composite films is significantly improved.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 23, 2022
    Inventors: JIA-LIN SYU, YING-HUNG CHEN, PING-YEN HSIEH, CHU-LIANG HO
  • Publication number: 20220095444
    Abstract: The present invention discloses a plasma aerosol device, comprising a gas tunnel, a dielectric barrier discharge module, and a liquid tunnel. The invention uses a mechanism similar to a dielectric barrier discharge (DBD) electrode system, thus to enable generating a plasma active water mist which riches in free radicals such as reactive nitrogen species (RNS) and reactive oxygen species (ROS). Therefore, this invention is able to be used in medical, sterilization, agriculture and preservation industries.
    Type: Application
    Filed: December 15, 2020
    Publication date: March 24, 2022
    Inventors: GUAN-HENG LYU, YING-HUNG CHEN, PING-YEN HSIEH, TSUNG-HAN CHEN, CHU-LIANG HO