Abstract: A data transceiving system, comprising: a data receiving apparatus, comprising a data receiving side command pin and at least one data receiving side data pin; a data transmitting apparatus, comprising a data transmitting side command pin and at least one data transmitting side data pin. The data receiving apparatus transmits a first command signal from the data receiving side command pin to the data transmitting side command pin, and the data transmitting apparatus transmits a first response signal from the data transmitting side command pin to the data receiving side command pin. The data transmitting apparatus transmits data from the data transmitting side data pin to the data receiving side data pin. The data transmitting apparatus transmits a first data sampling clock signal from the data transmitting side command pin to the data receiving side command pin, to sample the data.

Abstract: A data transceiving system, comprising: a data receiving apparatus, comprising a data receiving side command pin and at least one data receiving side data pin; a data transmitting apparatus, comprising a data transmitting side command pin and at least one data transmitting side data pin. The data receiving apparatus transmits a first command signal from the data receiving side command pin to the data transmitting side command pin, and the data transmitting apparatus transmits a first response signal from the data transmitting side command pin to the data receiving side command pin. The data transmitting apparatus transmits data from the data transmitting side data pin to the data receiving side data pin. The data transmitting apparatus transmits a first data sampling clock signal from the data transmitting side command pin to the data receiving side command pin, to sample the data.

Abstract: A method for data transmission in a device coupled to a host via a bus is provided. A sequence of data packets are received from the host and the received data packets are stored into a buffering unit of the device. It is then determined whether a predetermined error has occurred. When the predetermined error has occurred, the buffering unit of the device is locked to stop receiving the data packets. Thereafter, the buffering unit of the device is unlocked according to an unlock request from the host to resume receiving subsequent data packets.

Abstract: The invention provides an electronic apparatus. In one embodiment, the electronic apparatus comprises a plurality of ports, an Ethernet circuit, a port switch, and a flow control scheduler. The Ethernet circuit generates a plurality of transmitted packets according to transmitted data sent from the host, and derives received data sent to a host from a plurality of received packets. The flow control scheduler receives a plurality of transmitting requests corresponding to the ports from the host, arbitrates between the transmitting requests corresponding to the ports to select a transmitting port from the ports, receives a plurality of receiving requests corresponding to the ports from the host, and arbitrates between the plurality of receiving requests corresponding to the ports to select a receiving port from the ports. The port switch sends the transmitted packets to the transmitting port, and receives the received packets from the receiving port.

Abstract: In a host-slave data transfer system, the slave device receives packet based data from an external device and stores the packet content in a buffer as data segments. The slave merges a plurality of data segments into data streams and transmits the data streams to the host. The host uses direct memory access (DMA) to unpack the data stream from the slave into individual data segments without memory copy. To enable the host to set up DMA, the slave transmits information regarding sizes of the data segments to the host beforehand via an outband channel, e.g. by transmitting the size information in headers and/or tailers inserted into previous data streams. The host utilizes the data segment size information to program descriptor tables, such that each descriptor in the descriptor tables causes one data segment in the data stream to be stored in the system memory of the host.

Abstract: The invention provides an electronic apparatus. In one embodiment, the electronic apparatus comprises a plurality of ports, an Ethernet circuit, a port switch, and a flow control scheduler. The Ethernet circuit generates a plurality of transmitted packets according to transmitted data sent from the host, and derives received data sent to a host from a plurality of received packets. The flow control scheduler receives a plurality of transmitting requests corresponding to the ports from the host, arbitrates between the transmitting requests corresponding to the ports to select a transmitting port from the ports, receives a plurality of receiving requests corresponding to the ports from the host, and arbitrates between the plurality of receiving requests corresponding to the ports to select a receiving port from the ports. The port switch sends the transmitted packets to the transmitting port, and receives the received packets from the receiving port.

Abstract: In a host-slave data transfer system, the slave device receives packet based data from an external device and stores the packet content in a buffer as data segments. The slave merges a plurality of data segments into data streams and transmits the data streams to the host. The host uses direct memory access (DMA) to unpack the data stream from the slave into individual data segments without memory copy. To enable the host to set up DMA, the slave transmits information regarding sizes of the data segments to the host beforehand via an outband channel, e.g. by transmitting the size information in headers and/or tailers inserted into previous data streams. The host utilizes the data segment size information to program descriptor tables, such that each descriptor in the descriptor tables causes one data segment in the data stream to be stored in the system memory of the host.

Abstract: A multi-queue single-FIFO scheme for quality of service oriented communication. According to the invention, an arbiter maintains a number of next access pointers for multiple queues storing data packets to be transmitted. The arbiter also determines which queue is to be serviced next contingent upon a quality of service policy and then fetches at least one data packet, identified by the chosen queue's next access pointer, through a peripheral bus by means of direct memory access (DMA). A single FIFO buffer is connected to the arbiter to store and manage the fetched data packet in a first-in-first-out manner. Following the FIFO buffer, physical layer interface logic accepts each data packet, if available, and prepares the data packet for transmission on a physical medium.

Abstract: A method for performing protocol data unit (PDU) header re-synchronization in a communication system includes: when a header check sequence (HCS) fail occurs, detecting whether there exists a valid HCS in a first portion of first data by utilizing at least one detection window, where the first data is derived from an input signal received by the communication system; and when a valid HCS is detected in the first portion of the first data, detecting whether at least a second portion of the first data matches a connection identifier (CID) to determine whether the PDU header re-synchronization is completed.

Abstract: A method for data transmission in a device coupled to a host via a bus is provided. A sequence of data packets are received from the host and the received data packets are stored into a buffering unit of the device. It is then determined whether a predetermined error has occurred. When the predetermined error has occurred, the buffering unit of the device is locked to stop receiving the data packets. Thereafter, the buffering unit of the device is unlocked according to an unlock request from the host to resume receiving subsequent data packets.

Abstract: In a host-slave data transfer system, the slave device transmits data regarding its status and buffer conditions to the host using tailers inserted into the data being transferred to the host. The slave device has a plurality of buffers, a buffer management circuit which manages the buffers and obtains buffer condition information (e.g. amount of available buffer space, amount of buffered data to be transferred to the host), a detection circuit which collects interrupt status of the slave, a processing circuit which generates headers or tailers containing the buffer conditions information and interrupt status, and a merging circuit which merges multiple data segments received from the data-source/data-destination device and associated headers and tailers to generate a stream of merged data. The host obtains the buffer condition information from the tailers, and uses it to determine the amount of data to transmit or receive from the slave.

Abstract: A method for performing protocol data unit (PDU) header re-synchronization in a communication system includes: when a header check sequence (HCS) fail occurs, detecting whether there exists a valid HCS in a first portion of first data by utilizing at least one detection window, where the first data is derived from an input signal received by the communication system; and when a valid HCS is detected in the first portion of the first data, detecting whether at least a second portion of the first data matches a connection identifier (CID) to determine whether the PDU header re-synchronization is completed.

Abstract: A scheme for performing secure communications in a wireless local network. In one aspect of the invention, software hosted on a host processing unit maintains multiple queues. A networking module adapted to communicate with the host processing unit includes corresponding FIFO buffers to service the queues. The networking module also comprises an arbiter and a security engine. The arbiter is responsible for determining which queue is to be serviced next contingent upon a priority scheme. The security engine preferably incorporates a cipher performing encryption and decryption in a sequential or chain mode. Once one of the queues is granted by the arbiter, the security engine fetches data from the granted queue and then encrypts or decrypts the data using the cipher.

Abstract: A multi-queue single-FIFO scheme for quality of service oriented communication. According to the invention, an arbiter maintains a number of next access pointers for multiple queues storing data packets to be transmitted. The arbiter also determines which queue is to be serviced next contingent upon a quality of service policy and then fetches at least one data packet, identified by the chosen queue's next access pointer, through a peripheral bus by means of direct memory access (DMA). A single FIFO buffer is connected to the arbiter to store and manage the fetched data packet in a first-in-first-out manner. Following the FIFO buffer, physical layer interface logic accepts each data packet, if available, and prepares the data packet for transmission on a physical medium.

Abstract: A multi-queue single-FIFO scheme for quality of service oriented communication. According to the invention, an arbiter maintains a number of next access pointers for multiple queues storing data packets to be transmitted. The arbiter also determines which queue is to be serviced next contingent upon a quality of service policy and then fetches at least one data packet, identified by the chosen queue's next access pointer, through a peripheral bus by means of direct memory access (DMA). A single FIFO buffer is connected to the arbiter to store and manage the fetched data packet in a first-in-first-out manner. Following the FIFO buffer, physical layer interface logic accepts each data packet, if available, and prepares the data packet for transmission on a physical medium.

Abstract: A polling-based communication apparatus and system. The apparatus of the invention, connected to a host computer through a peripheral bus, comprises an arbiter and multiple addressable entities. Each addressable entity corresponds to one of queues maintained in the host computer. The arbiter can determine which queue is to be served next in accordance with a quality of serve policy. The host computer polls each addressable entity by issuing a query packet. Depending on the queue chosen to be served next, the arbiter grants the corresponding addressable entity access to the peripheral bus, causing this granted addressable entity to respond to the host computer's polling with an acknowledgement packet. Thus the host computer initiates transactions to transfer data packets from the chosen queue through the peripheral bus to the corresponding addressable entity.

Abstract: A method and a device for detecting a preamble type of a wireless data frame are provided. The preamble has a synchronization (SYNC) field and a start frame delimiter (SFD) field, and the method comprises following steps. The wireless data frame is first received, and then determined whether the wireless data frame has a short preamble. When the wireless data frame has the short preamble, the wireless data frame is transmitted to a MAC device. In addition, if the wireless data frame does not have the short preamble, it determines whether the wireless data frame has a long preamble. When the wireless data frame has the long preamble, the wireless data frame is then transmitted to the MAC device.

Abstract: A scheme for performing secure communications in a wireless local network. In one aspect of the invention, software hosted on a host processing unit maintains multiple queues. A networking module adapted to communicate with the host processing unit includes corresponding FIFO buffers to service the queues. The networking module also comprises an arbiter and a security engine. The arbiter is responsible for determining which queue is to be serviced next contingent upon a priority scheme. The security engine preferably incorporates a cipher performing encryption and decryption in a sequential or chain mode. Once one of the queues is granted by the arbiter, the security engine fetches data from the granted queue and then encrypts or decrypts the data using the cipher.

Abstract: A polling-based communication apparatus and system. The apparatus of the invention, connected to a host computer through a peripheral bus, comprises an arbiter and multiple addressable entities. Each addressable entity corresponds to one of queues maintained in the host computer. The arbiter can determine which queue is to be served next in accordance with a quality of serve policy. The host computer polls each addressable entity by issuing a query packet. Depending on the queue chosen to be served next, the arbiter grants the corresponding addressable entity access to the peripheral bus, causing this granted addressable entity to respond to the host computer's polling with an acknowledgement packet. Thus the host computer initiates transactions to transfer data packets from the chosen queue through the peripheral bus to the corresponding addressable entity.

Abstract: A multi-queue single-FIFO scheme for quality of service oriented communication. According to the invention, an arbiter maintains a number of next access pointers for multiple queues storing data packets to be transmitted. The arbiter also determines which queue is to be serviced next contingent upon a quality of service policy and then fetches at least one data packet, identified by the chosen queue's next access pointer, through a peripheral bus by means of direct memory access (DMA). A single FIFO buffer is connected to the arbiter to store and manage the fetched data packet in a first-in-first-out manner. Following the FIFO buffer, physical layer interface logic accepts each data packet, if available, and prepares the data packet for transmission on a physical medium.