Abstract: Defining an oxide define region (ODR) without using a photomask is disclosed. Pad oxide and a stop layer are deposited over peaks of a substrate of a semiconductor wafer. The pad oxide may be silicon oxide, whereas the stop layer may be silicon nitride. Oxide, such as high-density plasma (HDP) oxide, is deposited over the pad oxide, the stop layer, and valleys of the substrate of the semiconductor wafer. A hard mask, such as silicon nitride, is deposited over the oxide, and photoresist is deposited over the hard mask. The photoresist is etched back until peaks of the hard mask are exposed. The peaks of the hard mask and the oxide underneath are etched through to the stop layer, and the photoresist is removed. Chemical-mechanical planarization (CMP) can then be performed on the hard mask that remains and the oxide underneath through to the stop layer, and the stop layer removed.

Abstract: A pad open structure, after an insulation layer is installed at the up of the pad, the insulation layer forms plural pad opens by lithography. The insulation layer is exposed to the surface of the pad by the pad opens. The gold bump forms the upper part of the insulation layer, which forms an electric connection through the pad opens to the pad. By way of this, when the gold bump is formed at the surface of the pad opens and the surrounding insulation layer, reducing the affection produced by a single pad open that hollows the surface of the gold bump such that the gold bump has an extra flat surface.

Abstract: The present invention relates to a method of whole-chip electrostatic discharge protection, wherein the chip has a first metallic layer and a second metallic layer, and each surrounds the chip along the trail keeping an appropriate spacing away from the perimeter of the chip separately, and in contrast to the first type semiconductor substrate, a second type semiconductor well is formed below the first metallic layer. The second type semiconductor well, which surrounds the chip along the trail keeping an appropriate spacing away from the perimeter of the chip, can function as a large capacitor to store the discharged electricity. Thereby, the electrostatic discharge protection of the whole chip can be promoted with no increasing chip area needed and without changing the original design and manufacture process of IC.

Abstract: The removal of defect particles that may be created during polysilicon hard mask etching, and that are embedded within the polysilicon layer, is disclosed. Oxide is first grown in the polysilicon layer exposed through the patterned hard mask layer, so that the defect particle becomes embedded within the oxide. Oxide growth may be accomplished by rapid thermal oxidation (RTO). The oxide is then exposed to an acidic solution, such as hydrofluoric (HF) acid, to remove the oxide and the embedded defect particle embedded therein.

Abstract: A method of making a microelectronic device providing a base substrate having a bond pad, a first passivation layer overlying the base substrate and a portion of the bond pad, and a second passivation layer overlying the first passivation layer; forming a first sacrificial layer over the second passivation layer, wherein the first sacrificial layer includes an opening therethrough; etching the exposed portion of the second passivation layer to provide a recess therein; trimming a portion of the first sacrificial layer to enlarge the opening; etching the exposed portion of the second passivation layer to provide an enlarged recess and a first riser, a second tread, a second riser and a second tread; removing the first sacrificial layer; depositing a redistribution layer into the enlarged recess in the second passivation layer and over the first riser, first tread, second riser, and second tread.

Abstract: The removal of defect particles that may be created during polysilicon hard mask etching, and that are embedded within the polysilicon layer, is disclosed. Oxide is first grown in the polysilicon layer exposed through the patterned hard mask layer, so that the defect particle becomes embedded within the oxide. Oxide growth may be accomplished by rapid thermal oxidation (RTO). The oxide is then exposed to an acidic solution, such as hydrofluoric (HF) acid, to remove the oxide and the embedded defect particle embedded therein.

Abstract: A method of making a microelectronic device providing a base substrate having a bond pad, a first passivation layer overlying the base substrate and a portion of the bond pad, and a second passivation layer overlying the first passivation layer; forming a first sacrificial layer over the second passivation layer, wherein the first sacrificial layer includes an opening therethrough; etching the exposed portion of the second passivation layer to provide a recess therein; trimming a portion of the first sacrificial layer to enlarge the opening; etching the exposed portion of the second passivation layer to provide an enlarged recess and a first riser, a second tread, a second riser and a second tread; removing the first sacrificial layer; depositing a redistribution layer into the enlarged recess in the second passivation layer and over the first riser, first tread, second riser, and second tread.

Abstract: Defining an oxide define region (ODR) without using a photomask is disclosed. Pad oxide and a stop layer are deposited over peaks of a substrate of a semiconductor wafer. The pad oxide may be silicon oxide, whereas the stop layer may be silicon nitride. Oxide, such as high-density plasma (HDP) oxide, is deposited over the pad oxide, the stop layer, and valleys of the substrate of the semiconductor wafer. A hard mask, such as silicon nitride, is deposited over the oxide, and photoresist is deposited over the hard mask. The photoresist is etched back until peaks of the hard mask are exposed. The peaks of the hard mask and the oxide underneath are etched through to the stop layer, and the photoresist is removed. Chemical-mechanical planarization (CMP) can then be performed on the hard mask that remains and the oxide underneath through to the stop layer, and the stop layer removed.