Patents by Inventor Chu-We Hu

Chu-We Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7101748
    Abstract: The fabrication an NMOS device featuring a shallow source/drain region, performed as part of an integrated process sequence employed to integrate the fabrication of other type devices with the fabrication of the NMOS device, has been developed. A critical feature of the integrated process sequence is the formation of the shallow source/drain region of the NMOS accomplished after formation of the other type devices, thus reducing the risk of exposure of the shallow source/drain region to possible damaging procedures used for the other type devices. In addition the process used to remove a photoresist shape, used to protect the completed other type devices from the shallow source/drain ion implantation procedure, has been modified again to reduce possible damage to the shallow source/drain region.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: September 5, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Lung Yeh, Chu-We Hu, Li-Te Hsu, Pin-Chia Su
  • Publication number: 20050191802
    Abstract: The fabrication an NMOS device featuring a shallow source/drain region, performed as part of an integrated process sequence employed to integrate the fabrication of other type devices with the fabrication of the NMOS device, has been developed. A critical feature of the integrated process sequence is the formation of the shallow source/drain region of the NMOS accomplished after formation of the other type devices, thus reducing the risk of exposure of the shallow source/drain region to possible damaging procedures used for the other type devices. In addition the process used to remove a photoresist shape, used to protect the completed other type devices from the shallow source/drain ion implantation procedure, has been modified again to reduce possible damage to the shallow source/drain region.
    Type: Application
    Filed: February 26, 2004
    Publication date: September 1, 2005
    Inventors: Yu-Lung Yeh, Chu-We Hu, Li-Te Hsu, Pin-Chia Su
  • Patent number: 6756671
    Abstract: A method of making a microelectronic device providing a base substrate having a bond pad, a first passivation layer overlying the base substrate and a portion of the bond pad, and a second passivation layer overlying the first passivation layer; forming a first sacrificial layer over the second passivation layer, wherein the first sacrificial layer includes an opening therethrough; etching the exposed portion of the second passivation layer to provide a recess therein; trimming a portion of the first sacrificial layer to enlarge the opening; etching the exposed portion of the second passivation layer to provide an enlarged recess and a first riser, a second tread, a second riser and a second tread; removing the first sacrificial layer; depositing a redistribution layer into the enlarged recess in the second passivation layer and over the first riser, first tread, second riser, and second tread.
    Type: Grant
    Filed: July 5, 2002
    Date of Patent: June 29, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chu-Sheng Lee, Chu-We Hu, Yu-Lung Yeh, Sheng-Hung Chou