Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.

Abstract: The present invention discloses an organic polymer film and a manufacturing method thereof. The organic polymer film is mainly manufactured by the following steps. Firstly, the step (A) provides a xylene precursor and a substrate, and the step (B) places the substrate inside of a plasma equipment. After that, the step (C) evacuates the plasma equipment while introducing a carrier gas which carries vapor of the xylene precursor, and the step (D) turns on a pulse power supply system of the plasma equipment, generating a short pulse for plasma ignition. Finally, the step (E) forms the organic polymer film on the substrate. In the aforementioned steps, the frequency of the short pulse plasma is between 1 Hz˜10,000 Hz, and the pulse period of the short pulse plasma is between 1 ?s˜60 ?s.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.

Abstract: The present disclosure describes a semiconductor structure having bonded wafers with storage layers and a method to bond wafers with storage layers. The semiconductor structure includes a first wafer including a first storage layer with carbon, a second wafer including a second storage layer with carbon, and a bonding layer interposed between the first and second wafers and in contact with the first and second storage layers.

Abstract: A method for forming a Dynamic Random Access Memory (DRAM) includes forming an isolation structure in a substrate to define an active region. The method also includes forming a bit line trench in the active region to divide two active pillars. The method also includes forming a buried bit line in the bit line trench. The method also includes forming an insulating material over the bit line in the bit line trench. The top surface of the insulating material is lower than the top surface of the substrate. A trench is formed over the insulating material. The method also includes forming a shallow recess on the sidewalls of each of the active pillars exposed by the trench to make that each of the active pillars has a neck channel region. The method also includes forming a buried word line in the shallow recess.

Abstract: A semiconductor memory structure includes an isolation structure surrounding an active region in a substrate. The structure also includes two word lines disposed in the active region. The structure also includes a bit line contact disposed between two word lines. The structure also includes a first bit line disposed over the bit line contact. The bit line contact includes polysilicon and has a concave top surface.

Abstract: A method and system for monitoring and controlling a semiconductor process are provided. The method includes: forming at least one active region on a substrate; forming a first patterned photoresist layer for defining at least two word lines on the active region after forming the active region; detecting and measuring positions and dimensions of the active region and the first patterned photoresist layer and calculating estimated areas of at least two estimated contact windows in the active region according to a predefined position of at least one bit line; adjusting the predefined position of the at least one bit line according to the estimated areas of the at least two estimated contact windows in the active region; and forming a second patterned photoresist layer on the substrate. The second patterned photoresist layer corresponds to the adjusted predefined position of the at least one bit line.

Abstract: A method of fabricating a memory device includes forming an oxide layer on a semiconductor substrate, and forming an isolation structure in the semiconductor substrate and the oxide layer to define an active area. The method also includes forming a word line and a bit line in the semiconductor substrate, wherein the bit line is above the word line. The method further includes removing the oxide layer to form a recess between the isolation structure and the bit line, and forming a storage node contact in the recess. In addition, from a top view, the storage node contact of the memory device overlaps a corresponding portion of the active area.

Abstract: A method for forming a semiconductor memory structure includes forming an isolation structure surrounding an active region in a substrate. The method also includes forming a first trench to separate the active region into a first active region and a second active region. The method also includes forming a bit line over the bottom portion of the first trench. The method also includes forming a word line surrounding the first active region and the second active region and over the bit line. The method also includes self-aligned forming a contact over the first active region and the second active region. The method also includes forming a capacitor over the contact.

Abstract: A method for forming a semiconductor memory structure includes forming an isolation structure surrounding an active region in a substrate. The method also includes forming a first trench to separate the active region into a first active region and a second active region. The method also includes forming a bit line over the bottom portion of the first trench. The method also includes forming a word line surrounding the first active region and the second active region and over the bit line. The method also includes self-aligned forming a contact over the first active region and the second active region. The method also includes forming a capacitor over the contact.

Abstract: A method of fabricating a memory device includes forming an oxide layer on a semiconductor substrate, and forming an isolation structure in the semiconductor substrate and the oxide layer to define an active area. The method also includes forming a word line and a bit line in the semiconductor substrate, wherein the bit line is above the word line. The method further includes removing the oxide layer to form a recess between the isolation structure and the bit line, and forming a storage node contact in the recess. In addition, from a top view, the storage node contact of the memory device overlaps a corresponding portion of the active area.

Abstract: A method of fabricating a memory device includes firming an oxide layer on a semiconductor substrate, and forming an isolation structure in the semiconductor substrate and the oxide layer to define an active area. The method also includes forming a word line and a bit line in the semiconductor substrate, wherein the bit line is above the word line. The method further includes removing the oxide layer to form a recess between the isolation structure and the bit line, and forming a storage node contact in the recess. In addition, from a top view, the storage node contact of the memory device overlaps a corresponding portion of the active area.

Abstract: A method of fabricating a memory device includes firming an oxide layer on a semiconductor substrate, and forming an isolation structure in the semiconductor substrate and the oxide layer to define an active area. The method also includes forming a word line and a bit line in the semiconductor substrate, wherein the bit line is above the word line. The method further includes removing the oxide layer to form a recess between the isolation structure and the bit line, and forming a storage node contact in the recess. In addition, from a top view, the storage node contact of the memory device overlaps a corresponding portion of the active area.

Abstract: A memory device includes a semiconductor substrate having at least one active area that is defined by a device isolation structure. The memory device further includes two neighboring buried word lines disposed in the semiconductor substrate of the active area. The memory device further includes a trench isolation structure disposed in the semiconductor substrate between the buried word lines.

Abstract: A battery charge apparatus and a charge system are disclosed. The charge apparatus includes first and second charge module connected to each other. The first charge module is connected to an auxiliary power, makes a processor thereof generate a charge-unit-address code for the charge unit thereof, and turns on an auxiliary switch thereof for transmitting the auxiliary power to the second charge module for activated the second charge module. The second charge module then sends a charge-module-address request to the first charge module to ask for a charge-module-address code. Thereafter, the first charge module performs charge procedure and informs the second charge module to perform charge procedure when battery connected to the first charge module is fully charged. The second charge module then performs charge procedure and sends fully charged information to the first charge module when the battery connected to the second charge module is fully charged.

Abstract: A memory device includes a semiconductor substrate having at least one active area that is defined by a device isolation structure. The memory device further includes two neighboring buried word lines disposed in the semiconductor substrate of the active area. The memory device further includes a trench isolation structure disposed in the semiconductor substrate between the buried word lines.

Abstract: A battery charge apparatus and a charge system are disclosed. The charge apparatus includes first and second charge module connected to each other. The first charge module is connected to an auxiliary power, makes a processor thereof generate a charge-unit-address code for the charge unit thereof, and turns on an auxiliary switch thereof for transmitting the auxiliary power to the second charge module for activated the second charge module. The second charge module then sends a charge-module-address request to the first charge module to ask for a charge-module-address code. Thereafter, the first charge module performs charge procedure and informs the second charge module to perform charge procedure when battery connected to the first charge module is fully charged. The second charge module then performs charge procedure and sends fully charged information to the first charge module when the battery connected to the second charge module is fully charged.

Abstract: A collar for pets includes an adjustment belt and a neck belt wherein the adjustment belt has a plurality of engagement holes equidistantly distributed at the surface of one side thereon, and the neck belt is provided with an engaging hoop attached at one side thereto. At the other side of the adjustment belt and the neck belt are respectively disposed a first and a second coupling hoops with a first and a second movable coupling belts attached at the other side of the coupling hoops thereof. The first/second movable coupling belts are respectively provided with a D-shaped first/second leash hoops at the outer side of the other end thereof, and a first/second passages disposed at the middle section thereon for holding a male and female buckle pieces with elastic buckling legs and buckling holes disposed thereon respectively.

Abstract: A nonlinear operation method suitable for audio encoding/decoding and an applied hardware thereof. The nonlinear operation method suitable for audio encoding exists in a quantization process for the audio encoding. The nonlinear operation equation is ƒ(X)=X3/4, where X represents the frequency-field data. The method comprises following steps. Building a query table that comprises the frequency-field data X and the corresponding value f(X) that corresponds to the frequency-field data X, wherein the query table is represented as a function T(X), and T(X)=X3/4, 1≦X ≦S, where S represents a data range included in the query table. Analyzing and providing a modified error quantity function fa(z) represented by an equation of power of 2, where z = ⌊ X 16 n ⌋ , n=1, 2 or 3, so that z falls in the data range S.